Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * cbe_regs.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * This file is intended to hold the various register definitions for CBE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * on-chip system devices (memory controller, IO controller, etc...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * (C) Copyright IBM Corporation 2001,2006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Authors: Maximino Aguilar (maguilar@us.ibm.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *          David J. Erb (djerb@us.ibm.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #ifndef CBE_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define CBE_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/cell-pmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * Some HID register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* CBE specific HID0 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define HID0_CBE_THERM_WAKEUP	0x0000020000000000ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define HID0_CBE_SYSERR_WAKEUP	0x0000008000000000ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define HID0_CBE_THERM_INT_EN	0x0000000400000000ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define HID0_CBE_SYSERR_INT_EN	0x0000000200000000ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MAX_CBE		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * Pervasive unit register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) union spe_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	u8 spe[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) union ppe_spe_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		u32 ppe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		u32 spe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) struct cbe_pmd_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	/* Debug Bus Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u64	pad_0x0000;					/* 0x0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u64	group_control;					/* 0x0008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u8	pad_0x0010_0x00a8 [0x00a8 - 0x0010];		/* 0x0010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u64	debug_bus_control;				/* 0x00a8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u8	pad_0x00b0_0x0100 [0x0100 - 0x00b0];		/* 0x00b0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	u64	trace_aux_data;					/* 0x0100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u64	trace_buffer_0_63;				/* 0x0108 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u64	trace_buffer_64_127;				/* 0x0110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u64	trace_address;					/* 0x0118 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u64	ext_tr_timer;					/* 0x0120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u8	pad_0x0128_0x0400 [0x0400 - 0x0128];		/* 0x0128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	/* Performance Monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u64	pm_status;					/* 0x0400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u64	pm_control;					/* 0x0408 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u64	pm_interval;					/* 0x0410 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u64	pm_ctr[4];					/* 0x0418 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u64	pm_start_stop;					/* 0x0438 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u64	pm07_control[8];				/* 0x0440 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u8	pad_0x0480_0x0800 [0x0800 - 0x0480];		/* 0x0480 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* Thermal Sensor Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	union	spe_reg	ts_ctsr1;				/* 0x0800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u64	ts_ctsr2;					/* 0x0808 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	union	spe_reg	ts_mtsr1;				/* 0x0810 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u64	ts_mtsr2;					/* 0x0818 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	union	spe_reg	ts_itr1;				/* 0x0820 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u64	ts_itr2;					/* 0x0828 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u64	ts_gitr;					/* 0x0830 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u64	ts_isr;						/* 0x0838 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u64	ts_imr;						/* 0x0840 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	union	spe_reg	tm_cr1;					/* 0x0848 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u64	tm_cr2;						/* 0x0850 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u64	tm_simr;					/* 0x0858 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	union	ppe_spe_reg tm_tpr;				/* 0x0860 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	union	spe_reg	tm_str1;				/* 0x0868 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u64	tm_str2;					/* 0x0870 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	union	ppe_spe_reg tm_tsr;				/* 0x0878 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* Power Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u64	pmcr;						/* 0x0880 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CBE_PMD_PAUSE_ZERO_CONTROL	0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	u64	pmsr;						/* 0x0888 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	/* Time Base Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	u64	tbr;						/* 0x0890 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	u8	pad_0x0898_0x0c00 [0x0c00 - 0x0898];		/* 0x0898 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* Fault Isolation Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	u64	checkstop_fir;					/* 0x0c00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	u64	recoverable_fir;				/* 0x0c08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u64	spec_att_mchk_fir;				/* 0x0c10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u32	fir_mode_reg;					/* 0x0c18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u8	pad_0x0c1c_0x0c20 [4];				/* 0x0c1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CBE_PMD_FIR_MODE_M8		0x00800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	u64	fir_enable_mask;				/* 0x0c20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u8	pad_0x0c28_0x0ca8 [0x0ca8 - 0x0c28];		/* 0x0c28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u64	ras_esc_0;					/* 0x0ca8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u8	pad_0x0cb0_0x1000 [0x1000 - 0x0cb0];		/* 0x0cb0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  * PMU shadow registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * Many of the registers in the performance monitoring unit are write-only,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  * so we need to save a copy of what we write to those registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  * The actual data counters are read/write. However, writing to the counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  * only takes effect if the PMU is enabled. Otherwise the value is stored in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  * a hardware latch until the next time the PMU is enabled. So we save a copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  * of the counter values if we need to read them back while the PMU is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  * disabled. The counter_value_in_latch field is a bitmap indicating which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  * counters currently have a value waiting to be written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct cbe_pmd_shadow_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	u32 group_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	u32 debug_bus_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	u32 trace_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	u32 ext_tr_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	u32 pm_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	u32 pm_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	u32 pm_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32 pm_start_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	u32 pm07_control[NR_CTRS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u32 pm_ctr[NR_PHYS_CTRS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u32 counter_value_in_latch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) extern struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) extern struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * IIC unit register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct cbe_iic_pending_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u8 class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u8 source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u8 prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CBE_IIC_IRQ_VALID	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CBE_IIC_IRQ_IPI		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct cbe_iic_thread_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct cbe_iic_pending_bits pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct cbe_iic_pending_bits pending_destr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u64 generate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u64 prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct cbe_iic_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	u8	pad_0x0000_0x0400[0x0400 - 0x0000];		/* 0x0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* IIC interrupt registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct	cbe_iic_thread_regs thread[2];			/* 0x0400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	u64	iic_ir;						/* 0x0440 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CBE_IIC_IR_PRIO(x)      (((x) & 0xf) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CBE_IIC_IR_DEST_NODE(x) (((x) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CBE_IIC_IR_DEST_UNIT(x) ((x) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CBE_IIC_IR_IOC_0        0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CBE_IIC_IR_IOC_1S       0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CBE_IIC_IR_PT_0         0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CBE_IIC_IR_PT_1         0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	u64	iic_is;						/* 0x0448 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CBE_IIC_IS_PMI		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	u8	pad_0x0450_0x0500[0x0500 - 0x0450];		/* 0x0450 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	/* IOC FIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	u64	ioc_fir_reset;					/* 0x0500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	u64	ioc_fir_set;					/* 0x0508 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u64	ioc_checkstop_enable;				/* 0x0510 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	u64	ioc_fir_error_mask;				/* 0x0518 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	u64	ioc_syserr_enable;				/* 0x0520 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	u64	ioc_fir;					/* 0x0528 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	u8	pad_0x0530_0x1000[0x1000 - 0x0530];		/* 0x0530 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct cbe_mic_tm_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	u8	pad_0x0000_0x0040[0x0040 - 0x0000];		/* 0x0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	u64	mic_ctl_cnfg2;					/* 0x0040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CBE_MIC_ENABLE_AUX_TRC		0x8000000000000000LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CBE_MIC_DISABLE_PWR_SAV_2	0x0200000000000000LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CBE_MIC_DISABLE_AUX_TRC_WRAP	0x0100000000000000LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CBE_MIC_ENABLE_AUX_TRC_INT	0x0080000000000000LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	u64	pad_0x0048;					/* 0x0048 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	u64	mic_aux_trc_base;				/* 0x0050 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	u64	mic_aux_trc_max_addr;				/* 0x0058 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	u64	mic_aux_trc_cur_addr;				/* 0x0060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	u64	mic_aux_trc_grf_addr;				/* 0x0068 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	u64	mic_aux_trc_grf_data;				/* 0x0070 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	u64	pad_0x0078;					/* 0x0078 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	u64	mic_ctl_cnfg_0;					/* 0x0080 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CBE_MIC_DISABLE_PWR_SAV_0	0x8000000000000000LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	u64	pad_0x0088;					/* 0x0088 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	u64	slow_fast_timer_0;				/* 0x0090 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	u64	slow_next_timer_0;				/* 0x0098 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	u8	pad_0x00a0_0x00f8[0x00f8 - 0x00a0];		/* 0x00a0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	u64    	mic_df_ecc_address_0;				/* 0x00f8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	u8	pad_0x0100_0x01b8[0x01b8 - 0x0100];		/* 0x0100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	u64    	mic_df_ecc_address_1;				/* 0x01b8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	u64	mic_ctl_cnfg_1;					/* 0x01c0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CBE_MIC_DISABLE_PWR_SAV_1	0x8000000000000000LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	u64	pad_0x01c8;					/* 0x01c8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	u64	slow_fast_timer_1;				/* 0x01d0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	u64	slow_next_timer_1;				/* 0x01d8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	u8	pad_0x01e0_0x0208[0x0208 - 0x01e0];		/* 0x01e0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	u64	mic_exc;					/* 0x0208 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CBE_MIC_EXC_BLOCK_SCRUB		0x0800000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CBE_MIC_EXC_FAST_SCRUB		0x0100000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	u64	mic_mnt_cfg;					/* 0x0210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CBE_MIC_MNT_CFG_CHAN_0_POP	0x0002000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CBE_MIC_MNT_CFG_CHAN_1_POP	0x0004000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	u64	mic_df_config;					/* 0x0218 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CBE_MIC_ECC_DISABLE_0		0x4000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CBE_MIC_ECC_REP_SINGLE_0	0x2000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CBE_MIC_ECC_DISABLE_1		0x0080000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CBE_MIC_ECC_REP_SINGLE_1	0x0040000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	u8	pad_0x0220_0x0230[0x0230 - 0x0220];		/* 0x0220 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	u64	mic_fir;					/* 0x0230 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CBE_MIC_FIR_ECC_SINGLE_0_ERR	0x0200000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CBE_MIC_FIR_ECC_MULTI_0_ERR	0x0100000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CBE_MIC_FIR_ECC_SINGLE_1_ERR	0x0080000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CBE_MIC_FIR_ECC_MULTI_1_ERR	0x0040000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CBE_MIC_FIR_ECC_ERR_MASK	0xffff000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CBE_MIC_FIR_ECC_SINGLE_0_CTE	0x0000020000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CBE_MIC_FIR_ECC_MULTI_0_CTE	0x0000010000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CBE_MIC_FIR_ECC_SINGLE_1_CTE	0x0000008000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CBE_MIC_FIR_ECC_MULTI_1_CTE	0x0000004000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CBE_MIC_FIR_ECC_CTE_MASK	0x0000ffff00000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CBE_MIC_FIR_ECC_SINGLE_0_RESET	0x0000000002000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CBE_MIC_FIR_ECC_MULTI_0_RESET	0x0000000001000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CBE_MIC_FIR_ECC_SINGLE_1_RESET	0x0000000000800000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CBE_MIC_FIR_ECC_MULTI_1_RESET	0x0000000000400000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define CBE_MIC_FIR_ECC_RESET_MASK	0x00000000ffff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define CBE_MIC_FIR_ECC_SINGLE_0_SET	0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CBE_MIC_FIR_ECC_MULTI_0_SET	0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CBE_MIC_FIR_ECC_SINGLE_1_SET	0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CBE_MIC_FIR_ECC_MULTI_1_SET	0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CBE_MIC_FIR_ECC_SET_MASK	0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	u64	mic_fir_debug;					/* 0x0238 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	u8	pad_0x0240_0x1000[0x1000 - 0x0240];		/* 0x0240 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Cell page table entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CBE_IOPTE_PP_W		0x8000000000000000ul /* protection: write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CBE_IOPTE_PP_R		0x4000000000000000ul /* protection: read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CBE_IOPTE_M		0x2000000000000000ul /* coherency required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define CBE_IOPTE_SO_R		0x1000000000000000ul /* ordering: writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CBE_IOPTE_SO_RW		0x1800000000000000ul /* ordering: r & w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CBE_IOPTE_RPN_Mask	0x07fffffffffff000ul /* RPN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CBE_IOPTE_H		0x0000000000000800ul /* cache hint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CBE_IOPTE_IOID_Mask	0x00000000000007fful /* ioid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* some utility functions to deal with SMT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) extern u32 cbe_get_hw_thread_id(int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) extern u32 cbe_cpu_to_node(int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) extern u32 cbe_node_to_cpu(int node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Init this module early */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) extern void cbe_regs_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #endif /* CBE_REGS_H */