^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cell Broadband Engine Performance Monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) Copyright IBM Corporation 2006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * David Erb (djerb@us.ibm.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Kevin Corry (kevcorry@us.ibm.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __ASM_CELL_PMU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __ASM_CELL_PMU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* The Cell PMU has four hardware performance counters, which can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * configured as four 32-bit counters or eight 16-bit counters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define NR_PHYS_CTRS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define NR_CTRS (NR_PHYS_CTRS * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Macros for the pm_control register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CBE_PM_ENABLE_PERF_MON 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CBE_PM_STOP_AT_MAX 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CBE_PM_TRACE_MODE_GET(pm_control) (((pm_control) >> 28) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CBE_PM_TRACE_MODE_SET(mode) (((mode) & 0x3) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CBE_PM_TRACE_BUF_OVFLW(bit) (((bit) & 0x1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CBE_PM_COUNT_MODE_SET(count) (((count) & 0x3) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CBE_PM_FREEZE_ALL_CTRS 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CBE_PM_ENABLE_EXT_TRACE 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CBE_PM_SPU_ADDR_TRACE_SET(msk) (((msk) & 0x3) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Macros for the trace_address register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CBE_PM_TRACE_BUF_FULL 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CBE_PM_TRACE_BUF_EMPTY 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CBE_PM_TRACE_BUF_DATA_COUNT(ta) ((ta) & 0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CBE_PM_TRACE_BUF_MAX_COUNT 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Macros for the pm07_control registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CBE_PM_CTR_INPUT_MUX(pm07_control) (((pm07_control) >> 26) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CBE_PM_CTR_INPUT_CONTROL 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CBE_PM_CTR_POLARITY 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CBE_PM_CTR_COUNT_CYCLES 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CBE_PM_CTR_ENABLE 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PM07_CTR_INPUT_MUX(x) (((x) & 0x3F) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PM07_CTR_INPUT_CONTROL(x) (((x) & 1) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PM07_CTR_POLARITY(x) (((x) & 1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PM07_CTR_COUNT_CYCLES(x) (((x) & 1) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PM07_CTR_ENABLE(x) (((x) & 1) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Macros for the pm_status register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) enum pm_reg_name {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) group_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) debug_bus_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) trace_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ext_tr_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pm_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pm_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pm_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pm_start_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Routines for reading/writing the PMU registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) extern u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) extern u32 cbe_read_ctr(u32 cpu, u32 ctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern u32 cbe_read_pm07_control(u32 cpu, u32 ctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) extern u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) extern u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) extern void cbe_enable_pm(u32 cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) extern void cbe_disable_pm(u32 cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) extern void cbe_read_trace_buffer(u32 cpu, u64 *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) extern void cbe_disable_pm_interrupts(u32 cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) extern u32 cbe_get_and_clear_pm_interrupts(u32 cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) extern void cbe_sync_irq(int node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CBE_COUNT_SUPERVISOR_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CBE_COUNT_HYPERVISOR_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CBE_COUNT_PROBLEM_MODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CBE_COUNT_ALL_MODES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #endif /* __ASM_CELL_PMU_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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