^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_POWERPC_CACHE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_POWERPC_CACHE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* bytes per L1 cache line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #if defined(CONFIG_PPC_8xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define L1_CACHE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MAX_COPY_PREFETCH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IFETCH_ALIGN_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #elif defined(CONFIG_PPC_E500MC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define L1_CACHE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MAX_COPY_PREFETCH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IFETCH_ALIGN_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #elif defined(CONFIG_PPC32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MAX_COPY_PREFETCH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IFETCH_ALIGN_SHIFT 3 /* 603 fetches 2 insn at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #if defined(CONFIG_PPC_47x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define L1_CACHE_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define L1_CACHE_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #else /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define L1_CACHE_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IFETCH_ALIGN_SHIFT 4 /* POWER8,9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SMP_CACHE_BYTES L1_CACHE_BYTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IFETCH_ALIGN_BYTES (1 << IFETCH_ALIGN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #if !defined(__ASSEMBLY__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct ppc_cache_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 block_size; /* L1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 log_block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 blocks_per_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 sets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 assoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct ppc64_caches {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct ppc_cache_info l1d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct ppc_cache_info l1i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct ppc_cache_info l2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct ppc_cache_info l3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) extern struct ppc64_caches ppc64_caches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static inline u32 l1_dcache_shift(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return ppc64_caches.l1d.log_block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline u32 l1_dcache_bytes(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return ppc64_caches.l1d.block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static inline u32 l1_icache_shift(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return ppc64_caches.l1i.log_block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline u32 l1_icache_bytes(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return ppc64_caches.l1i.block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static inline u32 l1_dcache_shift(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return L1_CACHE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static inline u32 l1_dcache_bytes(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return L1_CACHE_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline u32 l1_icache_shift(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return L1_CACHE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static inline u32 l1_icache_bytes(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return L1_CACHE_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define __read_mostly __section(".data..read_mostly")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #ifdef CONFIG_PPC_BOOK3S_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) extern long _get_L2CR(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) extern long _get_L3CR(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) extern void _set_L2CR(unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) extern void _set_L3CR(unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define _get_L2CR() 0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define _get_L3CR() 0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define _set_L2CR(val) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define _set_L3CR(val) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline void dcbz(void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline void dcbi(void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static inline void dcbf(void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) __asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static inline void dcbst(void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static inline void icbi(void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) asm volatile ("icbi 0, %0" : : "r"(addr) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static inline void iccci(void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) asm volatile ("iccci 0, %0" : : "r"(addr) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif /* !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #endif /* _ASM_POWERPC_CACHE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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