^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SHA-1 implementation for PowerPC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005 Paul Mackerras <paulus@samba.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/ppc_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/asm-compat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifdef __BIG_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define LWZ(rt, d, ra) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) lwz rt,d(ra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define LWZ(rt, d, ra) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) li rt,d; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) lwbrx rt,rt,ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * We roll the registers for T, A, B, C, D, E around on each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * iteration; T on iteration t is A on iteration t+1, and so on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * We use registers 7 - 12 for this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RT(t) ((((t)+5)%6)+7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RA(t) ((((t)+4)%6)+7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RB(t) ((((t)+3)%6)+7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RC(t) ((((t)+2)%6)+7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RD(t) ((((t)+1)%6)+7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RE(t) ((((t)+0)%6)+7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* We use registers 16 - 31 for the W values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define W(t) (((t)%16)+16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LOADW(t) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) LWZ(W(t),(t)*4,r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define STEPD0_LOAD(t) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) andc r0,RD(t),RB(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) and r6,RB(t),RC(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) rotlwi RT(t),RA(t),5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) or r6,r6,r0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) add r0,RE(t),r15; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) add RT(t),RT(t),r6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) add r14,r0,W(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) LWZ(W((t)+4),((t)+4)*4,r4); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) rotlwi RB(t),RB(t),30; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) add RT(t),RT(t),r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define STEPD0_UPDATE(t) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) and r6,RB(t),RC(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) andc r0,RD(t),RB(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) rotlwi RT(t),RA(t),5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) rotlwi RB(t),RB(t),30; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) or r6,r6,r0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) add r0,RE(t),r15; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) xor r5,W((t)+4-3),W((t)+4-8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) add RT(t),RT(t),r6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) xor W((t)+4),W((t)+4-16),W((t)+4-14); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) add r0,r0,W(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) xor W((t)+4),W((t)+4),r5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) add RT(t),RT(t),r0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) rotlwi W((t)+4),W((t)+4),1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define STEPD1(t) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) xor r6,RB(t),RC(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) rotlwi RT(t),RA(t),5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) rotlwi RB(t),RB(t),30; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) xor r6,r6,RD(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) add r0,RE(t),r15; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) add RT(t),RT(t),r6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) add r0,r0,W(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) add RT(t),RT(t),r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define STEPD1_UPDATE(t) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) xor r6,RB(t),RC(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) rotlwi RT(t),RA(t),5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) rotlwi RB(t),RB(t),30; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) xor r6,r6,RD(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) add r0,RE(t),r15; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) xor r5,W((t)+4-3),W((t)+4-8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) add RT(t),RT(t),r6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) xor W((t)+4),W((t)+4-16),W((t)+4-14); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) add r0,r0,W(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) xor W((t)+4),W((t)+4),r5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) add RT(t),RT(t),r0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) rotlwi W((t)+4),W((t)+4),1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define STEPD2_UPDATE(t) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) and r6,RB(t),RC(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) and r0,RB(t),RD(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) rotlwi RT(t),RA(t),5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) or r6,r6,r0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) rotlwi RB(t),RB(t),30; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) and r0,RC(t),RD(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) xor r5,W((t)+4-3),W((t)+4-8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) or r6,r6,r0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) xor W((t)+4),W((t)+4-16),W((t)+4-14); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) add r0,RE(t),r15; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) add RT(t),RT(t),r6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) add r0,r0,W(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) xor W((t)+4),W((t)+4),r5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) add RT(t),RT(t),r0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) rotlwi W((t)+4),W((t)+4),1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define STEP0LD4(t) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) STEPD0_LOAD(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) STEPD0_LOAD((t)+1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) STEPD0_LOAD((t)+2); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) STEPD0_LOAD((t)+3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define STEPUP4(t, fn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) STEP##fn##_UPDATE(t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) STEP##fn##_UPDATE((t)+1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) STEP##fn##_UPDATE((t)+2); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) STEP##fn##_UPDATE((t)+3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define STEPUP20(t, fn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) STEPUP4(t, fn); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) STEPUP4((t)+4, fn); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) STEPUP4((t)+8, fn); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) STEPUP4((t)+12, fn); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) STEPUP4((t)+16, fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) _GLOBAL(powerpc_sha_transform)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PPC_STLU r1,-INT_FRAME_SIZE(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SAVE_8GPRS(14, r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SAVE_10GPRS(22, r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Load up A - E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) lwz RA(0),0(r3) /* A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) lwz RB(0),4(r3) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) lwz RC(0),8(r3) /* C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) lwz RD(0),12(r3) /* D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) lwz RE(0),16(r3) /* E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) LOADW(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) LOADW(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) LOADW(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) LOADW(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) lis r15,0x5a82 /* K0-19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ori r15,r15,0x7999
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) STEP0LD4(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) STEP0LD4(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) STEP0LD4(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) STEPUP4(12, D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) STEPUP4(16, D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) lis r15,0x6ed9 /* K20-39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ori r15,r15,0xeba1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) STEPUP20(20, D1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) lis r15,0x8f1b /* K40-59 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ori r15,r15,0xbcdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) STEPUP20(40, D2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) lis r15,0xca62 /* K60-79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ori r15,r15,0xc1d6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) STEPUP4(60, D1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) STEPUP4(64, D1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) STEPUP4(68, D1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) STEPUP4(72, D1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) lwz r20,16(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) STEPD1(76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) lwz r19,12(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) STEPD1(77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) lwz r18,8(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) STEPD1(78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) lwz r17,4(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) STEPD1(79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) lwz r16,0(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) add r20,RE(80),r20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) add RD(0),RD(80),r19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) add RC(0),RC(80),r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) add RB(0),RB(80),r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) add RA(0),RA(80),r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mr RE(0),r20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) stw RA(0),0(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) stw RB(0),4(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) stw RC(0),8(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) stw RD(0),12(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) stw RE(0),16(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) REST_8GPRS(14, r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) REST_10GPRS(22, r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) addi r1,r1,INT_FRAME_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) blr
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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