Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Common registers for PPC AES implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2015 Markus Stockhausen <stockhausen@collogia.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define rKS r0	/* copy of en-/decryption key pointer			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define rDP r3	/* destination pointer					*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define rSP r4	/* source pointer					*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define rKP r5	/* pointer to en-/decryption key pointer		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define rRR r6	/* en-/decryption rounds				*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define rLN r7	/* length of data to be processed			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define rIP r8	/* potiner to IV (CBC/CTR/XTS modes)			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define rKT r9	/* pointer to tweak key (XTS mode)			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define rT0 r11	/* pointers to en-/decryption tables			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define rT1 r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define rD0 r9	/* data 						*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define rD1 r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define rD2 r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define rD3 r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define rW0 r16	/* working registers					*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define rW1 r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define rW2 r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define rW3 r19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define rW4 r20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define rW5 r21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define rW6 r22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define rW7 r23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define rI0 r24	/* IV							*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define rI1 r25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define rI2 r26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define rI3 r27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define rG0 r28	/* endian reversed tweak (XTS mode)			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define rG1 r29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define rG2 r30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define rG3 r31