Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * arch/powerpc/boot/wii-head.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Nintendo Wii bootwrapper entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2008-2009 The GameCube Linux Team
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2008,2009 Albert Herranz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include "ppc_asm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * The entry code does no assumptions regarding:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * - if the data and instruction caches are enabled or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * - if the MMU is enabled or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * - if the high BATs are enabled or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * We enable the high BATs, enable the caches if not already enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * enable the MMU with an identity mapping scheme and jump to the start code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	.globl _zimage_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) _zimage_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	/* turn the MMU off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	mfmsr	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	rlwinm	9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	bcl	20, 31, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	mflr	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	clrlwi	8, 8, 3		/* convert to a real address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	addi	8, 8, _mmu_off - 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	mtsrr0	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	mtsrr1	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) _mmu_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	/* MMU disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	/* setup BATs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	li      8, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	mtspr	0x210, 8	/* IBAT0U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	mtspr	0x212, 8	/* IBAT1U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	mtspr	0x214, 8	/* IBAT2U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	mtspr	0x216, 8	/* IBAT3U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	mtspr	0x218, 8	/* DBAT0U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	mtspr	0x21a, 8	/* DBAT1U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	mtspr	0x21c, 8	/* DBAT2U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	mtspr	0x21e, 8	/* DBAT3U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	mtspr	0x230, 8	/* IBAT4U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	mtspr	0x232, 8	/* IBAT5U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	mtspr	0x234, 8	/* IBAT6U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	mtspr	0x236, 8	/* IBAT7U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	mtspr	0x238, 8	/* DBAT4U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	mtspr	0x23a, 8	/* DBAT5U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	mtspr	0x23c, 8	/* DBAT6U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	mtspr	0x23e, 8	/* DBAT7U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	li	8, 0x01ff	/* first 16MiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	li	9, 0x0002	/* rw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	mtspr	0x211, 9	/* IBAT0L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	mtspr	0x210, 8	/* IBAT0U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	mtspr	0x219, 9	/* DBAT0L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	mtspr	0x218, 8	/* DBAT0U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	lis	8, 0x0c00	/* I/O mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	ori	8, 8, 0x3ff	/* 32MiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	lis	9, 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	ori	9, 9, 0x002a	/* uncached, guarded, rw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	mtspr	0x21b, 9	/* DBAT1L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	mtspr	0x21a, 8	/* DBAT1U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	lis	8, 0x0100	/* next 8MiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	ori	8, 8, 0x00ff	/* 8MiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	lis	9, 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	ori	9, 9, 0x0002	/* rw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	mtspr	0x215, 9	/* IBAT2L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	mtspr	0x214, 8	/* IBAT2U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	mtspr	0x21d, 9	/* DBAT2L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	mtspr	0x21c, 8	/* DBAT2U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	lis	8, 0x1000	/* MEM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	ori	8, 8, 0x07ff	/* 64MiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	lis	9, 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	ori	9, 9, 0x0002	/* rw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	mtspr	0x216, 8	/* IBAT3U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	mtspr	0x217, 9	/* IBAT3L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	mtspr	0x21e, 8	/* DBAT3U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	mtspr	0x21f, 9	/* DBAT3L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	/* enable the high BATs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	mfspr	8, 0x3f3	/* HID4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	oris	8, 8, 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	mtspr	0x3f3, 8	/* HID4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/* enable and invalidate the caches if not already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	mfspr	8, 0x3f0	/* HID0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	andi.	0, 8, (1<<15)		/* HID0_ICE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	bne	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	ori	8, 8, (1<<15)|(1<<11)	/* HID0_ICE|HID0_ICFI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	andi.	0, 8, (1<<14)		/* HID0_DCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	bne	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	ori	8, 8, (1<<14)|(1<<10)	/* HID0_DCE|HID0_DCFI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	mtspr	0x3f0, 8	/* HID0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	/* initialize arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	li	3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	li	4, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	li	5, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* turn the MMU on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	bcl	20, 31, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	mflr	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	addi	8, 8, _mmu_on - 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	mfmsr	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	ori	9, 9, (1<<4)|(1<<5) /* MSR_DR|MSR_IR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	mtsrr0	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	mtsrr1	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) _mmu_on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	/* turn on the front blue led (aka: yay! we got here!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	lis	8, 0x0d00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	ori	8, 8, 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	lwz	9, 0(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ori	9, 9, 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	stw	9, 0(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	b _zimage_start_lib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)