Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * PowerQUICC II support functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author: Scott Wood <scottwood@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (c) 2007 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "types.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "fsl-soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "pq2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "stdio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "io.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PQ2_SCCR (0x10c80/4) /* System Clock Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PQ2_SCMR (0x10c88/4) /* System Clock Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static int pq2_corecnf_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	3, 2, 2, 2, 4, 4, 5, 9, 6, 11, 8, 10, 3, 12, 7, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	6, 5, 13, 2, 14, 4, 15, 9, 0, 11, 8, 10, 16, 12, 7, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Get various clocks from crystal frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  * Returns zero on failure and non-zero on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int pq2_get_clocks(u32 crystal, u32 *sysfreq, u32 *corefreq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)                    u32 *timebase, u32 *brgfreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	u32 *immr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	u32 sccr, scmr, mainclk, busclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	int corecnf, busdf, plldf, pllmf, dfbrg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	immr = fsl_get_immr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	if (!immr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		printf("pq2_get_clocks: Couldn't get IMMR base.\r\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	sccr = in_be32(&immr[PQ2_SCCR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	scmr = in_be32(&immr[PQ2_SCMR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	dfbrg = sccr & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	corecnf = (scmr >> 24) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	busdf = (scmr >> 20) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	plldf = (scmr >> 12) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	pllmf = scmr & 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	mainclk = crystal * (pllmf + 1) / (plldf + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	busclk = mainclk / (busdf + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	if (sysfreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		*sysfreq = mainclk / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	if (timebase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		*timebase = busclk / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	if (brgfreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		*brgfreq = mainclk / (1 << ((dfbrg + 1) * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	if (corefreq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		int coremult = pq2_corecnf_map[corecnf];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		if (coremult < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 			*corefreq = mainclk / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		else if (coremult == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 			*corefreq = busclk * coremult / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Set common device tree fields based on the given clock frequencies. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void pq2_set_clocks(u32 sysfreq, u32 corefreq, u32 timebase, u32 brgfreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	void *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	dt_fixup_cpu_clocks(corefreq, timebase, sysfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	node = finddevice("/soc/cpm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	if (node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 		setprop(node, "clock-frequency", &sysfreq, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 	node = finddevice("/soc/cpm/brg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 	if (node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 		setprop(node, "clock-frequency", &brgfreq, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int pq2_fixup_clocks(u32 crystal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 	u32 sysfreq, corefreq, timebase, brgfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 	if (!pq2_get_clocks(crystal, &sysfreq, &corefreq, &timebase, &brgfreq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 	pq2_set_clocks(sysfreq, corefreq, timebase, brgfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }