^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This interface is used for compatibility with old U-boots *ONLY*.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Please do not imitate or extend this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (C) Copyright 2000, 2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __PPCBOOT_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __PPCBOOT_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Board information passed to kernel from PPCBoot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * include/asm-ppc/ppcboot.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "types.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) typedef struct bd_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned long bi_memstart; /* start of DRAM memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned long bi_memsize; /* size of DRAM memory in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned long bi_flashstart; /* start of FLASH memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned long bi_flashsize; /* size of FLASH memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned long bi_flashoffset; /* reserved area for startup monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long bi_sramstart; /* start of SRAM memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned long bi_sramsize; /* size of SRAM memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #if defined(TARGET_8xx) || defined(TARGET_CPM2) || defined(TARGET_85xx) ||\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) defined(TARGET_83xx) || defined(TARGET_86xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long bi_immr_base; /* base of IMMR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #if defined(TARGET_PPC_MPC52xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned long bi_mbar_base; /* base of internal registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long bi_ip_addr; /* IP Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned char bi_enetaddr[6]; /* Ethernet address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned long bi_intfreq; /* Internal Freq, in MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned long bi_busfreq; /* Bus Freq, in MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #if defined(TARGET_CPM2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long bi_vco; /* VCO Out from PLL, in MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #if defined(TARGET_PPC_MPC52xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long bi_baudrate; /* Console Baudrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #if defined(TARGET_4xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned char bi_s_version[4]; /* Version of this structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned char bi_r_version[32]; /* Version of the ROM (IBM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #if defined(TARGET_HYMOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) hymod_conf_t bi_hymod_conf; /* hymod configuration information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #if defined(TARGET_EVB64260) || defined(TARGET_405EP) || defined(TARGET_44x) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) defined(TARGET_85xx) || defined(TARGET_83xx) || defined(TARGET_HAS_ETH1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* second onboard ethernet port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned char bi_enet1addr[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HAVE_ENET1ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #if defined(TARGET_EVB64260) || defined(TARGET_440GX) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) defined(TARGET_85xx) || defined(TARGET_HAS_ETH2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* third onboard ethernet ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned char bi_enet2addr[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HAVE_ENET2ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #if defined(TARGET_440GX) || defined(TARGET_HAS_ETH3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* fourth onboard ethernet ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned char bi_enet3addr[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HAVE_ENET3ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #if defined(TARGET_4xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int bi_opbfreq; /* OB clock in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int bi_iic_fast[2]; /* Use fast i2c mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #if defined(TARGET_440GX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int bi_phynum[4]; /* phy mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int bi_phymode[4]; /* phy mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) } bd_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define bi_tbfreq bi_intfreq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif /* __PPCBOOT_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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