Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _PPC64_PPC_ASM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _PPC64_PPC_ASM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Definitions used by various bits of low-level assembly code on PowerPC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Condition Register Bit Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define	cr0	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define	cr1	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define	cr2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define	cr3	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define	cr4	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define	cr5	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define	cr6	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define	cr7	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* General Purpose Registers (GPRs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define	r0	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define	r1	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define	r2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define	r3	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define	r4	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define	r5	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define	r6	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define	r7	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define	r8	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define	r9	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define	r10	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define	r11	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define	r12	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define	r13	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define	r14	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define	r15	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define	r16	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define	r17	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define	r18	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define	r19	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define	r20	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define	r21	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define	r22	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define	r23	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define	r24	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define	r25	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define	r26	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define	r27	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define	r28	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define	r29	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define	r30	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define	r31	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPRN_TBRL	268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPRN_TBRU	269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPRN_HSRR0	0x13A	/* Hypervisor Save/Restore 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SPRN_HSRR1	0x13B	/* Hypervisor Save/Restore 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MSR_LE		0x0000000000000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FIXUP_ENDIAN						   \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	tdi   0,0,0x48;	  /* Reverse endian of b . + 8		*/ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	b     $+44;	  /* Skip trampoline if endian is good	*/ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	.long 0xa600607d; /* mfmsr r11				*/ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	.long 0x01006b69; /* xori r11,r11,1			*/ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	.long 0x00004039; /* li r10,0				*/ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	.long 0x6401417d; /* mtmsrd r10,1			*/ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	.long 0x05009f42; /* bcl 20,31,$+4			*/ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	.long 0xa602487d; /* mflr r10				*/ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	.long 0x14004a39; /* addi r10,r10,20			*/ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	.long 0xa6035a7d; /* mtsrr0 r10				*/ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	.long 0xa6037b7d; /* mtsrr1 r11				*/ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	.long 0x2400004c  /* rfid				*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #ifdef CONFIG_PPC_8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MFTBL(dest)			mftb dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MFTBU(dest)			mftbu dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MFTBL(dest)			mfspr dest, SPRN_TBRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MFTBU(dest)			mfspr dest, SPRN_TBRU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #endif /* _PPC64_PPC_ASM_H */