Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * 16550 serial console support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Original copied from <file:arch/ppc/boot/common/ns16550.c>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * (which had no copyright)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Modifications: 2006 (c) MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Modified by: Mark A. Greer <mgreer@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <stdarg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "types.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "string.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "stdio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "io.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "of.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define UART_DLL	0	/* Out: Divisor Latch Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define UART_DLM	1	/* Out: Divisor Latch High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define UART_FCR	2	/* Out: FIFO Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define UART_LCR	3	/* Out: Line Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define UART_MCR	4	/* Out: Modem Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define UART_LSR	5	/* In:  Line Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define UART_LSR_DR	0x01	/* Receiver data ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UART_MSR	6	/* In:  Modem Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UART_SCR	7	/* I/O: Scratch Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static unsigned char *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static u32 reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int ns16550_open(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	out_8(reg_base + (UART_FCR << reg_shift), 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void ns16550_putc(unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	out_8(reg_base, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static unsigned char ns16550_getc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	return in_8(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static u8 ns16550_tstc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int ns16550_console_init(void *devp, struct serial_console_data *scdp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	u32 reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	if (dt_get_virtual_reg(devp, (void **)&reg_base, 1) < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		printf("virt reg parse fail...\r\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	n = getprop(devp, "reg-offset", &reg_offset, sizeof(reg_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	if (n == sizeof(reg_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		reg_base += be32_to_cpu(reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	n = getprop(devp, "reg-shift", &reg_shift, sizeof(reg_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	if (n != sizeof(reg_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		reg_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 		reg_shift = be32_to_cpu(reg_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	scdp->open = ns16550_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	scdp->putc = ns16550_putc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	scdp->getc = ns16550_getc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	scdp->tstc = ns16550_tstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	scdp->close = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }