Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * MPC8xx support functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author: Scott Wood <scottwood@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (c) 2007 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "types.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "fsl-soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "mpc8xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "stdio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "io.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MPC8XX_PLPRCR (0x284/4) /* PLL and Reset Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Return system clock from crystal frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 mpc885_get_clock(u32 crystal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	u32 *immr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	u32 plprcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	int mfi, mfn, mfd, pdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	immr = fsl_get_immr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	if (!immr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		printf("mpc885_get_clock: Couldn't get IMMR base.\r\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	plprcr = in_be32(&immr[MPC8XX_PLPRCR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	mfi = (plprcr >> 16) & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	if (mfi < 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		printf("Warning: PLPRCR[MFI] value of %d out-of-bounds\r\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		       mfi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		mfi = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	pdf = (plprcr >> 1) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	mfd = (plprcr >> 22) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	mfn = (plprcr >> 27) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	ret = crystal * mfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	if (mfn != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		ret += crystal * mfn / (mfd + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	return ret / (pdf + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Set common device tree fields based on the given clock frequencies. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void mpc8xx_set_clocks(u32 sysclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	void *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	dt_fixup_cpu_clocks(sysclk, sysclk / 16, sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	node = finddevice("/soc/cpm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	if (node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		setprop(node, "clock-frequency", &sysclk, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	node = finddevice("/soc/cpm/brg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	if (node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		setprop(node, "clock-frequency", &sysclk, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int mpc885_fixup_clocks(u32 crystal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	u32 sysclk = mpc885_get_clock(crystal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	if (!sysclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	mpc8xx_set_clocks(sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }