Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * MPC5200 PSC serial console support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author: Grant Likely <grant.likely@secretlab.ca>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (c) 2007 Secret Lab Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (c) 2007 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * It is assumed that the firmware (or the platform file) has already set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * up the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "types.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "io.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Programmable Serial Controller (PSC) status register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MPC52xx_PSC_SR		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MPC52xx_PSC_SR_RXRDY		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MPC52xx_PSC_SR_RXFULL		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MPC52xx_PSC_SR_TXRDY		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MPC52xx_PSC_SR_TXEMP		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MPC52xx_PSC_BUFFER	0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void *psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int psc_open(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	/* Assume the firmware has already configured the PSC into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	 * uart mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void psc_putc(unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	while (!(in_be16(psc + MPC52xx_PSC_SR) & MPC52xx_PSC_SR_TXRDY)) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	out_8(psc + MPC52xx_PSC_BUFFER, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static unsigned char psc_tstc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	return (in_be16(psc + MPC52xx_PSC_SR) & MPC52xx_PSC_SR_RXRDY) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static unsigned char psc_getc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	while (!(in_be16(psc + MPC52xx_PSC_SR) & MPC52xx_PSC_SR_RXRDY)) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	return in_8(psc + MPC52xx_PSC_BUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	/* Get the base address of the psc registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	if (dt_get_virtual_reg(devp, &psc, 1) < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	scdp->open = psc_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	scdp->putc = psc_putc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	scdp->getc = psc_getc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	scdp->tstc = psc_tstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }