^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/powerpc/boot/gamecube-head.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Nintendo GameCube bootwrapper entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004-2009 The GameCube Linux Team
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008,2009 Albert Herranz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "ppc_asm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The entry code does no assumptions regarding:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * - if the data and instruction caches are enabled or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * - if the MMU is enabled or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * We enable the caches if not already enabled, enable the MMU with an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * identity mapping scheme and jump to the start code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .globl _zimage_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) _zimage_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* turn the MMU off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) mfmsr 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) bcl 20, 31, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) mflr 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) clrlwi 8, 8, 3 /* convert to a real address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) addi 8, 8, _mmu_off - 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) mtsrr0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) mtsrr1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) _mmu_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* MMU disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* setup BATs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) li 8, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) mtspr 0x210, 8 /* IBAT0U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mtspr 0x212, 8 /* IBAT1U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) mtspr 0x214, 8 /* IBAT2U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) mtspr 0x216, 8 /* IBAT3U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) mtspr 0x218, 8 /* DBAT0U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) mtspr 0x21a, 8 /* DBAT1U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) mtspr 0x21c, 8 /* DBAT2U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mtspr 0x21e, 8 /* DBAT3U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) li 8, 0x01ff /* first 16MiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) li 9, 0x0002 /* rw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) mtspr 0x211, 9 /* IBAT0L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) mtspr 0x210, 8 /* IBAT0U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mtspr 0x219, 9 /* DBAT0L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mtspr 0x218, 8 /* DBAT0U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) lis 8, 0x0c00 /* I/O mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ori 8, 8, 0x3ff /* 32MiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) lis 9, 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ori 9, 9, 0x002a /* uncached, guarded, rw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) mtspr 0x21b, 9 /* DBAT1L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mtspr 0x21a, 8 /* DBAT1U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) lis 8, 0x0100 /* next 8MiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ori 8, 8, 0x00ff /* 8MiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) lis 9, 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ori 9, 9, 0x0002 /* rw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mtspr 0x215, 9 /* IBAT2L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mtspr 0x214, 8 /* IBAT2U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) mtspr 0x21d, 9 /* DBAT2L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mtspr 0x21c, 8 /* DBAT2U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* enable and invalidate the caches if not already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mfspr 8, 0x3f0 /* HID0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) andi. 0, 8, (1<<15) /* HID0_ICE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) bne 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ori 8, 8, (1<<15)|(1<<11) /* HID0_ICE|HID0_ICFI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) andi. 0, 8, (1<<14) /* HID0_DCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) bne 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ori 8, 8, (1<<14)|(1<<10) /* HID0_DCE|HID0_DCFI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mtspr 0x3f0, 8 /* HID0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* initialize arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) li 3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) li 4, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) li 5, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* turn the MMU on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) bcl 20, 31, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mflr 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) addi 8, 8, _mmu_on - 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mfmsr 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ori 9, 9, (1<<4)|(1<<5) /* MSR_DR|MSR_IR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mtsrr0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mtsrr1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) _mmu_on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) b _zimage_start_lib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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