Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2007 David Gibson, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Based on earlier code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *   Copyright (C) Paul Mackerras 1997.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *   Matt Porter <mporter@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *   Copyright 2002-2005 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *   Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *   Copyright (c) 2003, 2004 Zultys Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <stdarg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "types.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "elf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "string.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "stdio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "page.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "io.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "dcr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "4xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "44x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static u8 *ebony_mac0, *ebony_mac1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EBONY_FPGA_PATH		"/plb/opb/ebc/fpga"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define	EBONY_FPGA_FLASH_SEL	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EBONY_SMALL_FLASH_PATH	"/plb/opb/ebc/small-flash"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void ebony_flashsel_fixup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	void *devp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	u32 reg[3] = {0x0, 0x0, 0x80000};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	u8 *fpga;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	u8 fpga_reg0 = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	devp = finddevice(EBONY_FPGA_PATH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	if (!devp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		fatal("Couldn't locate FPGA node %s\n\r", EBONY_FPGA_PATH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		fatal("%s has missing or invalid virtual-reg property\n\r",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		      EBONY_FPGA_PATH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	fpga_reg0 = in_8(fpga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	devp = finddevice(EBONY_SMALL_FLASH_PATH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	if (!devp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		fatal("Couldn't locate small flash node %s\n\r",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		      EBONY_SMALL_FLASH_PATH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	if (getprop(devp, "reg", reg, sizeof(reg)) != sizeof(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		fatal("%s has reg property of unexpected size\n\r",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		      EBONY_SMALL_FLASH_PATH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	/* Invert address bit 14 (IBM-endian) if FLASH_SEL fpga bit is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	if (fpga_reg0 & EBONY_FPGA_FLASH_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		reg[1] ^= 0x80000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	setprop(devp, "reg", reg, sizeof(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void ebony_fixups(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	// FIXME: sysclk should be derived by reading the FPGA registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	unsigned long sysclk = 33000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	ibm440gp_fixup_clocks(sysclk, 6 * 1843200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	ibm4xx_sdram_fixup_memsize();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	dt_fixup_mac_address_by_alias("ethernet0", ebony_mac0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	dt_fixup_mac_address_by_alias("ethernet1", ebony_mac1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	ebony_flashsel_fixup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void ebony_init(void *mac0, void *mac1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	platform_ops.fixups = ebony_fixups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	platform_ops.exit = ibm44x_dbcr_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	ebony_mac0 = mac0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 	ebony_mac1 = mac1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 	fdt_init(_dtb_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 	serial_console_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }