^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Device Tree for Bluestone (APM821xx) board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2010, Applied Micro Circuits Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Tirumala R Marri <tmarri@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /dts-v1/;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) model = "apm,bluestone";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) compatible = "apm,bluestone";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) dcr-parent = <&{/cpus/cpu@0}>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) aliases {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ethernet0 = &EMAC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) serial0 = &UART0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) serial1 = &UART1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) model = "PowerPC,apm821xx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) reg = <0x00000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) clock-frequency = <0>; /* Filled in by U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) timebase-frequency = <0>; /* Filled in by U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) i-cache-line-size = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) d-cache-line-size = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) i-cache-size = <32768>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) d-cache-size = <32768>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) dcr-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) dcr-access-method = "native";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) next-level-cache = <&L2C0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) memory {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) device_type = "memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) UIC0: interrupt-controller0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) compatible = "ibm,uic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) cell-index = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) dcr-reg = <0x0c0 0x009>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) UIC1: interrupt-controller1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) compatible = "ibm,uic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) cell-index = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) dcr-reg = <0x0d0 0x009>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) interrupt-parent = <&UIC0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) UIC2: interrupt-controller2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) compatible = "ibm,uic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) cell-index = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dcr-reg = <0x0e0 0x009>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) interrupt-parent = <&UIC0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) UIC3: interrupt-controller3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) compatible = "ibm,uic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) cell-index = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dcr-reg = <0x0f0 0x009>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) interrupt-parent = <&UIC0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) OCM: ocm@400040000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) compatible = "ibm,ocm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) cell-index = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* configured in U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) reg = <4 0x00040000 0x8000>; /* 32K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SDR0: sdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) compatible = "ibm,sdr-apm821xx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dcr-reg = <0x00e 0x002>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) CPR0: cpr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) compatible = "ibm,cpr-apm821xx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dcr-reg = <0x00c 0x002>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) L2C0: l2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dcr-reg = <0x020 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 0x030 0x008>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) cache-line-size = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) cache-size = <262144>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) interrupt-parent = <&UIC1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) interrupts = <11 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) plb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) compatible = "ibm,plb4";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) clock-frequency = <0>; /* Filled in by U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) SDRAM0: sdram {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) compatible = "ibm,sdram-apm821xx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dcr-reg = <0x010 0x002>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MAL0: mcmal {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) compatible = "ibm,mcmal2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) descriptor-memory = "ocm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dcr-reg = <0x180 0x062>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) num-tx-chans = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) num-rx-chans = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) interrupt-parent = <&UIC2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) interrupts = < /*TXEOB*/ 0x6 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*RXEOB*/ 0x7 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*SERR*/ 0x3 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*TXDE*/ 0x4 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*RXDE*/ 0x5 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) POB0: opb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) compatible = "ibm,opb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) clock-frequency = <0>; /* Filled in by U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) EBC0: ebc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) compatible = "ibm,ebc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dcr-reg = <0x012 0x002>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) clock-frequency = <0>; /* Filled in by U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* ranges property is supplied by U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ranges = < 0x00000003 0x00000000 0xe0000000 0x8000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) interrupts = <0x6 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) interrupt-parent = <&UIC1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) nor_flash@0,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) compatible = "amd,s29gl512n", "cfi-flash";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) bank-width = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) reg = <0x00000000 0x00000000 0x00400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) partition@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) label = "kernel";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) reg = <0x00000000 0x00180000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) partition@180000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) label = "env";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) reg = <0x00180000 0x00020000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) partition@1a0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) label = "u-boot";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) reg = <0x001a0000 0x00060000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ndfc@1,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) compatible = "ibm,ndfc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) reg = <0x00000003 0x00000000 0x00002000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ccr = <0x00001000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) bank-settings = <0x80002222>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* 2Gb Nand Flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) nand {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) partition@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) label = "firmware";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) reg = <0x00000000 0x00C00000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) partition@c00000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) label = "environment";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) reg = <0x00C00000 0x00B00000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) partition@1700000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) label = "kernel";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) reg = <0x01700000 0x00E00000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) partition@2500000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) label = "root";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) reg = <0x02500000 0x08200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) partition@a700000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) label = "device-tree";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) reg = <0x0A700000 0x00B00000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) partition@b200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) label = "config";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) reg = <0x0B200000 0x00D00000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) partition@bf00000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) label = "diag";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) reg = <0x0BF00000 0x00C00000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) partition@cb00000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) label = "vendor";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) reg = <0x0CB00000 0x3500000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) UART0: serial@ef600300 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) device_type = "serial";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) compatible = "ns16550";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) reg = <0xef600300 0x00000008>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) virtual-reg = <0xef600300>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) clock-frequency = <0>; /* Filled in by U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) current-speed = <0>; /* Filled in by U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) interrupt-parent = <&UIC1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) interrupts = <0x1 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) UART1: serial@ef600400 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) device_type = "serial";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) compatible = "ns16550";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) reg = <0xef600400 0x00000008>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) virtual-reg = <0xef600400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) clock-frequency = <0>; /* Filled in by U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) current-speed = <0>; /* Filled in by U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) interrupt-parent = <&UIC0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) interrupts = <0x1 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) IIC0: i2c@ef600700 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) compatible = "ibm,iic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) reg = <0xef600700 0x00000014>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) interrupt-parent = <&UIC0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) interrupts = <0x2 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) rtc@68 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) compatible = "st,m41t80";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) reg = <0x68>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) interrupt-parent = <&UIC0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) interrupts = <0x9 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) sttm@4C {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) compatible = "adm,adm1032";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) reg = <0x4C>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) interrupt-parent = <&UIC1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) IIC1: i2c@ef600800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) compatible = "ibm,iic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) reg = <0xef600800 0x00000014>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) interrupt-parent = <&UIC0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) interrupts = <0x3 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) RGMII0: emac-rgmii@ef601500 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) compatible = "ibm,rgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) reg = <0xef601500 0x00000008>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) has-mdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) TAH0: emac-tah@ef601350 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) compatible = "ibm,tah";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) reg = <0xef601350 0x00000030>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) EMAC0: ethernet@ef600c00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) device_type = "network";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) interrupt-parent = <&EMAC0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) interrupts = <0x0 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*Wake*/ 0x1 &UIC2 0x14 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) reg = <0xef600c00 0x000000c4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) local-mac-address = [000000000000]; /* Filled in by U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mal-device = <&MAL0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mal-tx-channel = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mal-rx-channel = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) cell-index = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) max-frame-size = <9000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) rx-fifo-size = <16384>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) tx-fifo-size = <2048>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) phy-mode = "rgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) phy-map = <0x00000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) rgmii-device = <&RGMII0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) rgmii-channel = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) tah-device = <&TAH0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) tah-channel = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) has-inverted-stacr-oc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) has-new-stacr-staopc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PCIE0: pcie@d00000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) primary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) port = <0x0>; /* port number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 0x0000000c 0x08010000 0x00001000>; /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dcr-reg = <0x100 0x020>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) sdr-base = <0x300>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Outbound ranges, one memory and one IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * later cannot be changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Inbound 2GB range starting at 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* This drives busses 40 to 0x7f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) bus-range = <0x40 0x7f>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Legacy interrupts (note the weird polarity, the bridge seems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * to invert PCIe legacy interrupts).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * We are de-swizzling here because the numbers are actually for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * port of the root complex virtual P2P bridge. But I want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * to avoid putting a node for it in the tree, so the numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * below are basically de-swizzled numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * The real slot is on idsel 0, so the swizzling is 1:1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) interrupt-map-mask = <0x0 0x0 0x0 0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) interrupt-map = <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MSI: ppc4xx-msi@C10000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) reg = < 0xC 0x10000000 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 0xC 0x10000000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) sdr-base = <0x36C>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) msi-data = <0x00004440>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) msi-mask = <0x0000ffe0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) interrupts =<0 1 2 3 4 5 6 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) interrupt-parent = <&MSI>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) msi-available-ranges = <0x0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) interrupt-map = <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 0 &UIC3 0x18 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 1 &UIC3 0x19 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 2 &UIC3 0x1A 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 3 &UIC3 0x1B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 4 &UIC3 0x1C 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 5 &UIC3 0x1D 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 6 &UIC3 0x1E 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 7 &UIC3 0x1F 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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