Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef _PPC_BOOT_DCR_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define _PPC_BOOT_DCR_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #define mfdcr(rn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 	({	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 		unsigned long rval; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 		asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 		rval; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 	})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define mtdcr(rn, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define mfdcrx(rn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	({	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 		unsigned long rval; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 		asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 		rval; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define mtdcrx(rn, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	({	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 		asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* 440GP/440GX SDRAM controller DCRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DCRN_SDRAM0_CFGADDR				0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DCRN_SDRAM0_CFGDATA				0x011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SDRAM0_READ(offset) ({\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	mfdcr(DCRN_SDRAM0_CFGDATA); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SDRAM0_WRITE(offset, data) ({\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	mtdcr(DCRN_SDRAM0_CFGDATA, data); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define 	SDRAM0_B0CR				0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define 	SDRAM0_B1CR				0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define 	SDRAM0_B2CR				0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define 	SDRAM0_B3CR				0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 					    SDRAM0_B2CR, SDRAM0_B3CR };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define			SDRAM_CONFIG_BANK_ENABLE        0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define			SDRAM_CONFIG_SIZE_MASK          0x000e0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define			SDRAM_CONFIG_BANK_SIZE(reg)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	(0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* 440GP External Bus Controller (EBC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DCRN_EBC0_CFGADDR				0x012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define DCRN_EBC0_CFGDATA				0x013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define   EBC_NUM_BANKS					  8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define   EBC_B0CR					  0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define   EBC_B1CR					  0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define   EBC_B2CR					  0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define   EBC_B3CR					  0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define   EBC_B4CR					  0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define   EBC_B5CR					  0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define   EBC_B6CR					  0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define   EBC_B7CR					  0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define   EBC_BXCR(n)					  (n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define	    EBC_BXCR_BAS				    0xfff00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define	    EBC_BXCR_BS				  	    0x000e0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define	    EBC_BXCR_BANK_SIZE(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	(0x100000 << (((reg) & EBC_BXCR_BS) >> 17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define	    EBC_BXCR_BU				  	    0x00018000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define	      EBC_BXCR_BU_OFF			  	      0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define	      EBC_BXCR_BU_RO			  	      0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define	      EBC_BXCR_BU_WO			  	      0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define	      EBC_BXCR_BU_RW			  	      0x00018000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define	    EBC_BXCR_BW				  	    0x00006000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define   EBC_B0AP					  0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define   EBC_B1AP					  0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define   EBC_B2AP					  0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define   EBC_B3AP					  0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define   EBC_B4AP					  0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define   EBC_B5AP					  0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define   EBC_B6AP					  0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define   EBC_B7AP					  0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define   EBC_BXAP(n)					  (0x10+(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define   EBC_BEAR					  0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define   EBC_BESR					  0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define   EBC_CFG					  0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define   EBC_CID					  0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* 440GP Clock, PM, chip control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define DCRN_CPC0_SR					0x0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define DCRN_CPC0_ER					0x0b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define DCRN_CPC0_FR					0x0b2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define DCRN_CPC0_SYS0					0x0e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define	  CPC0_SYS0_TUNE				  0xffc00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define	  CPC0_SYS0_FBDV_MASK				  0x003c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define	  CPC0_SYS0_FWDVA_MASK				  0x00038000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define	  CPC0_SYS0_FWDVB_MASK				  0x00007000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define	  CPC0_SYS0_OPDV_MASK				  0x00000c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define	  CPC0_SYS0_EPDV_MASK				  0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* Helper macros to compute the actual clock divider values from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * encodings in the CPC0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define	  CPC0_SYS0_FBDV(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		((((((reg) & CPC0_SYS0_FBDV_MASK) >> 18) - 1) & 0xf) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define	  CPC0_SYS0_FWDVA(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		(8 - (((reg) & CPC0_SYS0_FWDVA_MASK) >> 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define	  CPC0_SYS0_FWDVB(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		(8 - (((reg) & CPC0_SYS0_FWDVB_MASK) >> 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define	  CPC0_SYS0_OPDV(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		((((reg) & CPC0_SYS0_OPDV_MASK) >> 10) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define	  CPC0_SYS0_EPDV(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		((((reg) & CPC0_SYS0_EPDV_MASK) >> 8) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define	  CPC0_SYS0_EXTSL				  0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define	  CPC0_SYS0_RW_MASK				  0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define	  CPC0_SYS0_RL					  0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define	  CPC0_SYS0_ZMIISL_MASK				  0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define	  CPC0_SYS0_BYPASS				  0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define	  CPC0_SYS0_NTO1				  0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DCRN_CPC0_SYS1					0x0e1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DCRN_CPC0_CUST0					0x0e2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DCRN_CPC0_CUST1					0x0e3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DCRN_CPC0_STRP0					0x0e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DCRN_CPC0_STRP1					0x0e5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DCRN_CPC0_STRP2					0x0e6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DCRN_CPC0_STRP3					0x0e7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DCRN_CPC0_GPIO					0x0e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DCRN_CPC0_PLB					0x0e9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DCRN_CPC0_CR1					0x0ea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DCRN_CPC0_CR0					0x0eb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define	  CPC0_CR0_SWE					  0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define	  CPC0_CR0_CETE					  0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define	  CPC0_CR0_U1FCS				  0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define	  CPC0_CR0_U0DTE				  0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define	  CPC0_CR0_U0DRE				  0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define	  CPC0_CR0_U0DC					  0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define	  CPC0_CR0_U1DTE				  0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define	  CPC0_CR0_U1DRE				  0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define	  CPC0_CR0_U1DC					  0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define	  CPC0_CR0_U0EC					  0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define	  CPC0_CR0_U1EC					  0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define	  CPC0_CR0_UDIV_MASK				  0x001f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define	  CPC0_CR0_UDIV(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		((((reg) & CPC0_CR0_UDIV_MASK) >> 16) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DCRN_CPC0_MIRQ0					0x0ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DCRN_CPC0_MIRQ1					0x0ed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DCRN_CPC0_JTAGID				0x0ef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DCRN_MAL0_CFG					0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MAL_RESET 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* 440EP Clock/Power-on Reset regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DCRN_CPR0_ADDR	0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DCRN_CPR0_DATA	0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CPR0_PLLD0	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CPR0_OPBD0	0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CPR0_PERD0	0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CPR0_PRIMBD0	0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CPR0_SCPID	0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CPR0_PLLC0	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* 405GP Clocking/Power Management/Chip Control regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DCRN_CPC0_PLLMR 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DCRN_405_CPC0_CR0 0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DCRN_405_CPC0_CR1 0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DCRN_405_CPC0_PSR 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* 405EP Clocking/Power Management/Chip Control regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DCRN_CPC0_PLLMR0  0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DCRN_CPC0_PLLMR1  0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DCRN_CPC0_UCR     0xf5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* 440GX/405EX Clock Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DCRN_CPR0_CLKUPD				0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DCRN_CPR0_PLLC					0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DCRN_CPR0_PLLD					0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DCRN_CPR0_PRIMAD				0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DCRN_CPR0_PRIMBD				0x0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DCRN_CPR0_OPBD					0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DCRN_CPR0_PERD					0x0e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DCRN_CPR0_MALD					0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DCRN_SDR0_CONFIG_ADDR 	0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DCRN_SDR0_CONFIG_DATA	0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* SDR read/write helper macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SDR0_READ(offset) ({\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	mfdcr(DCRN_SDR0_CONFIG_DATA); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SDR0_WRITE(offset, data) ({\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DCRN_SDR0_UART0		0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DCRN_SDR0_UART1		0x0121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DCRN_SDR0_UART2		0x0122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DCRN_SDR0_UART3		0x0123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DCRN_CPR0_CFGADDR				0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DCRN_CPR0_CFGDATA				0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CPR0_READ(offset) ({\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	mtdcr(DCRN_CPR0_CFGADDR, offset); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	mfdcr(DCRN_CPR0_CFGDATA); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CPR0_WRITE(offset, data) ({\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	mtdcr(DCRN_CPR0_CFGADDR, offset); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	mtdcr(DCRN_CPR0_CFGDATA, data); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #endif	/* _PPC_BOOT_DCR_H_ */