Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Old U-boot compatibility for PowerQUICC II
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * (a.k.a. 82xx with CPM, not the 8240 family of chips)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Scott Wood <scottwood@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (c) 2007 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "stdio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "cuboot.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "io.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "fsl-soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define TARGET_CPM2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define TARGET_HAS_ETH1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "ppcboot.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static bd_t bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) struct cs_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	u32 csnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u32 base; /* must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) struct pci_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32 pci_addr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u32 phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u32 size[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) struct cs_range cs_ranges_buf[MAX_PROP_LEN / sizeof(struct cs_range)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) struct pci_range pci_ranges_buf[MAX_PROP_LEN / sizeof(struct pci_range)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* Different versions of u-boot put the BCSR in different places, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * some don't set up the PCI PIC at all, so we assume the device tree is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * sane and update the BRx registers appropriately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * For any node defined as compatible with fsl,pq2-localbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * #address/#size must be 2/1 for the localbus, and 1/1 for the parent bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * Ranges must be for whole chip selects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static void update_cs_ranges(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	void *bus_node, *parent_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u32 *ctrl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	unsigned long ctrl_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	u32 naddr, nsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	bus_node = finddevice("/localbus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-localbus"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	dt_get_reg_format(bus_node, &naddr, &nsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (naddr != 2 || nsize != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	parent_node = get_parent(bus_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	if (!parent_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	dt_get_reg_format(parent_node, &naddr, &nsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (naddr != 1 || nsize != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	if (!dt_xlate_reg(bus_node, 0, (unsigned long *)&ctrl_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	                  &ctrl_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	len = getprop(bus_node, "ranges", cs_ranges_buf, sizeof(cs_ranges_buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	for (i = 0; i < len / sizeof(struct cs_range); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		u32 base, option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		int cs = cs_ranges_buf[i].csnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		if (cs >= ctrl_size / 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		if (cs_ranges_buf[i].base != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		base = in_be32(&ctrl_addr[cs * 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		/* If CS is already valid, use the existing flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		 * Otherwise, guess a sane default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		if (base & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			base &= 0x7fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			base = 0x1801;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			option = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		out_be32(&ctrl_addr[cs * 2], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		out_be32(&ctrl_addr[cs * 2 + 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		         option | ~(cs_ranges_buf[i].size - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	printf("Bad /localbus node\r\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Older u-boots don't set PCI up properly.  Update the hardware to match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  * the device tree.  The prefetch mem region and non-prefetch mem region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * must be contiguous in the host bus.  As required by the PCI binding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  * PCI #addr/#size must be 3/2.  The parent bus must be 1/1.  Only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  * 32-bit PCI is supported.  All three region types (prefetchable mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  * non-prefetchable mem, and I/O) must be present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void fixup_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct pci_range *mem = NULL, *mmio = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	                 *io = NULL, *mem_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u32 *pci_regs[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u8 *soc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	int i, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	void *node, *parent_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u32 naddr, nsize, mem_pow2, mem_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	node = finddevice("/pci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (!node || !dt_is_compatible(node, "fsl,pq2-pci"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		if (!dt_xlate_reg(node, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		                  (unsigned long *)&pci_regs[i], NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	soc_regs = (u8 *)fsl_get_immr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (!soc_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		goto unhandled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	dt_get_reg_format(node, &naddr, &nsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (naddr != 3 || nsize != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	parent_node = get_parent(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (!parent_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	dt_get_reg_format(parent_node, &naddr, &nsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (naddr != 1 || nsize != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		goto unhandled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	len = getprop(node, "ranges", pci_ranges_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	              sizeof(pci_ranges_buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	for (i = 0; i < len / sizeof(struct pci_range); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		u32 flags = pci_ranges_buf[i].flags & 0x43000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		if (flags == 0x42000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			mem = &pci_ranges_buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		else if (flags == 0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			mmio = &pci_ranges_buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		else if (flags == 0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			io = &pci_ranges_buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (!mem || !mmio || !io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		goto unhandled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (mem->size[1] != mmio->size[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		goto unhandled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (mem->size[1] & (mem->size[1] - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		goto unhandled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (io->size[1] & (io->size[1] - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		goto unhandled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (mem->phys_addr + mem->size[1] == mmio->phys_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		mem_base = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		mem_base = mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		goto unhandled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	out_be32(&pci_regs[1][0], mem_base->phys_addr | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	out_be32(&pci_regs[1][1], io->phys_addr | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	out_be32(&pci_regs[2][1], ~(io->size[1] - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	out_le32(&pci_regs[0][0], mem->pci_addr[1] >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	out_le32(&pci_regs[0][2], mem->phys_addr >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	out_le32(&pci_regs[0][4], (~(mem->size[1] - 1) >> 12) | 0xa0000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	out_le32(&pci_regs[0][6], mmio->pci_addr[1] >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	out_le32(&pci_regs[0][8], mmio->phys_addr >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	out_le32(&pci_regs[0][10], (~(mmio->size[1] - 1) >> 12) | 0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	out_le32(&pci_regs[0][12], io->pci_addr[1] >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	out_le32(&pci_regs[0][14], io->phys_addr >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	out_le32(&pci_regs[0][16], (~(io->size[1] - 1) >> 12) | 0xc0000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/* Inbound translation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	out_le32(&pci_regs[0][58], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	out_le32(&pci_regs[0][60], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	mem_pow2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	mem_mask = ~(mem_pow2 - 1) >> 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	out_le32(&pci_regs[0][62], 0xa0000000 | mem_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/* If PCI is disabled, drive RST high to enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (!(in_le32(&pci_regs[0][32]) & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		 /* Tpvrh (Power valid to RST# high) 100 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		udelay(100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		out_le32(&pci_regs[0][32], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		/* Trhfa (RST# high to first cfg access) 2^25 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		udelay(1020000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/* Enable bus master and memory access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	out_le32(&pci_regs[0][64], 0x80000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	out_le32(&pci_regs[0][65], in_le32(&pci_regs[0][65]) | 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/* Park the bus on PCI, and elevate PCI's arbitration priority,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 * as required by section 9.6 of the user's manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	out_8(&soc_regs[0x10028], 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	out_be32((u32 *)&soc_regs[0x1002c], 0x01236745);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	printf("Bad PCI node -- using existing firmware setup.\r\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unhandled:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	printf("Unsupported PCI node -- using existing firmware setup.\r\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void pq2_platform_fixups(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	void *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	node = finddevice("/soc/cpm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		setprop(node, "clock-frequency", &bd.bi_cpmfreq, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	node = finddevice("/soc/cpm/brg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		setprop(node, "clock-frequency",  &bd.bi_brgfreq, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	update_cs_ranges();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	fixup_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)                    unsigned long r6, unsigned long r7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	CUBOOT_INIT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	fdt_init(_dtb_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	serial_console_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	platform_ops.fixups = pq2_platform_fixups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }