^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * CPM serial console support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2007 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Scott Wood <scottwood@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * It is assumed that the firmware (or the platform file) has already set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * up the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "types.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "io.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "page.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct cpm_scc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 gsmrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 gsmrh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u16 psmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u8 res1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u16 todr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u16 dsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u16 scce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u8 res2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u16 sccm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u8 res3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 sccs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 res4[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct cpm_smc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 res1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u16 smcmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 res2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 smce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 res3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 smcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 res4[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct cpm_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u16 rbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u16 tbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u8 rfcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u8 tfcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u16 mrblr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 rstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 res1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u16 rbptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 res2[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 tstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 res3[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u16 tbptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 res4[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u16 maxidl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u16 idlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u16 brkln;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u16 brkec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u16 brkcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u16 rmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 res5[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct cpm_bd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u16 sc; /* Status and Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u16 len; /* Data length in buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 *addr; /* Buffer address in host memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void *cpcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct cpm_param *param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct cpm_smc *smc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct cpm_scc *scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct cpm_bd *tbdf, *rbdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static u32 cpm_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static void *cbd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static u32 cbd_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void (*do_cmd)(int op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void (*enable_port)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void (*disable_port)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CPM_CMD_STOP_TX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CPM_CMD_RESTART_TX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CPM_CMD_INIT_RX_TX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void cpm1_cmd(int op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) while (in_be16(cpcr) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) out_be16(cpcr, (op << 8) | cpm_cmd | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) while (in_be16(cpcr) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void cpm2_cmd(int op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) while (in_be32(cpcr) & 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) out_be32(cpcr, op | cpm_cmd | 0x10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) while (in_be32(cpcr) & 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void smc_disable_port(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) do_cmd(CPM_CMD_STOP_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) out_be16(&smc->smcmr, in_be16(&smc->smcmr) & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void scc_disable_port(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) do_cmd(CPM_CMD_STOP_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) & ~0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void smc_enable_port(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) out_be16(&smc->smcmr, in_be16(&smc->smcmr) | 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) do_cmd(CPM_CMD_RESTART_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void scc_enable_port(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) | 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) do_cmd(CPM_CMD_RESTART_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int cpm_serial_open(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) disable_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) out_8(¶m->rfcr, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) out_8(¶m->tfcr, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) out_be16(¶m->mrblr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) out_be16(¶m->maxidl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) out_be16(¶m->brkec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) out_be16(¶m->brkln, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) out_be16(¶m->brkcr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) rbdf = cbd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) rbdf->addr = (u8 *)rbdf - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) rbdf->sc = 0xa000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) rbdf->len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) tbdf = rbdf + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) tbdf->addr = (u8 *)rbdf - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) tbdf->sc = 0x2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tbdf->len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) sync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) out_be16(¶m->rbase, cbd_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) out_be16(¶m->tbase, cbd_offset + sizeof(struct cpm_bd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) do_cmd(CPM_CMD_INIT_RX_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) enable_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void cpm_serial_putc(unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) while (tbdf->sc & 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) sync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) tbdf->addr[0] = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) eieio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) tbdf->sc |= 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static unsigned char cpm_serial_tstc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return !(rbdf->sc & 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static unsigned char cpm_serial_getc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned char c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) while (!cpm_serial_tstc())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) sync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) c = rbdf->addr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) eieio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rbdf->sc |= 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int cpm_console_init(void *devp, struct serial_console_data *scdp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void *vreg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 reg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int is_smc = 0, is_cpm2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void *parent, *muram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void *muram_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned long muram_offset, muram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (dt_is_compatible(devp, "fsl,cpm1-smc-uart")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) is_smc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) } else if (dt_is_compatible(devp, "fsl,cpm2-scc-uart")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) is_cpm2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) } else if (dt_is_compatible(devp, "fsl,cpm2-smc-uart")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) is_cpm2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) is_smc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (is_smc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) enable_port = smc_enable_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) disable_port = smc_disable_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) enable_port = scc_enable_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) disable_port = scc_disable_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (is_cpm2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) do_cmd = cpm2_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) do_cmd = cpm1_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (getprop(devp, "fsl,cpm-command", &cpm_cmd, 4) < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (dt_get_virtual_reg(devp, vreg, 2) < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (is_smc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) smc = vreg[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) scc = vreg[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) param = vreg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) parent = get_parent(devp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (dt_get_virtual_reg(parent, &cpcr, 1) < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) muram = finddevice("/soc/cpm/muram/data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!muram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* For bootwrapper-compatible device trees, we assume that the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * entry has at least 128 bytes, and that #address-cells/#data-cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * is one for both parent and child.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (dt_get_virtual_reg(muram, &muram_addr, 1) < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (getprop(muram, "reg", reg, 8) < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) muram_offset = reg[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) muram_size = reg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Store the buffer descriptors at the end of the first muram chunk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * For SMC ports on CPM2-based platforms, relocate the parameter RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * just before the buffer descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) cbd_offset = muram_offset + muram_size - 2 * sizeof(struct cpm_bd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (is_cpm2 && is_smc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u16 *smc_base = (u16 *)param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u16 pram_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pram_offset = cbd_offset - 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pram_offset = _ALIGN_DOWN(pram_offset, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) disable_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) out_be16(smc_base, pram_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) param = muram_addr - muram_offset + pram_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) cbd_addr = muram_addr - muram_offset + cbd_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) scdp->open = cpm_serial_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) scdp->putc = cpm_serial_putc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) scdp->getc = cpm_serial_getc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) scdp->tstc = cpm_serial_tstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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