^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2007 David Gibson, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on earlier code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Matt Porter <mporter@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2002-2005 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (c) 2003, 2004 Zultys Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2009 Wind River Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Updated for supporting PPC405EX on Kilauea.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Tiejun Chen <tiejun.chen@windriver.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "types.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "string.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "stdio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "dcr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static unsigned long chip_11_errata(unsigned long memsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned long pvr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) pvr = mfpvr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) switch (pvr & 0xf0000ff0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) case 0x40000850:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) case 0x400008d0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) case 0x200008d0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) memsize -= 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Read the 4xx SDRAM controller to get size of system memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void ibm4xx_sdram_fixup_memsize(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned long memsize, bank_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) memsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) bank_config = SDRAM0_READ(sdram_bxcr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) memsize = chip_11_errata(memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) dt_fixup_memory(0, memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Read the 440SPe MQ controller to get size of system memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DCRN_MQ0_B0BAS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DCRN_MQ0_B1BAS 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DCRN_MQ0_B2BAS 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DCRN_MQ0_B3BAS 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static u64 ibm440spe_decode_bas(u32 bas)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u64 base = ((u64)(bas & 0xFFE00000u)) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* open coded because I'm paranoid about invalid values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) switch ((bas >> 4) & 0xFFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case 0xffc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return base + 0x000800000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case 0xff8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return base + 0x001000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case 0xff0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return base + 0x002000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case 0xfe0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return base + 0x004000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case 0xfc0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return base + 0x008000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case 0xf80:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return base + 0x010000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case 0xf00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return base + 0x020000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case 0xe00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return base + 0x040000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case 0xc00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return base + 0x080000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case 0x800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return base + 0x100000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) printf("Memory BAS value 0x%08x unsupported !\n", bas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void ibm440spe_fixup_memsize(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u64 banktop, memsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Ultimately, we should directly construct the memory node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * so we are able to handle holes in the memory address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (banktop > memsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) memsize = banktop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (banktop > memsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) memsize = banktop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (banktop > memsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) memsize = banktop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (banktop > memsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) memsize = banktop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dt_fixup_memory(0, memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* 4xx DDR1/2 Denali memory controller support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* DDR0 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DDR0_02 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DDR0_08 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DDR0_10 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DDR0_14 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DDR0_42 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DDR0_43 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* DDR0_02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DDR_START 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DDR_START_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DDR_MAX_CS_REG 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DDR_MAX_CS_REG_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DDR_MAX_COL_REG 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DDR_MAX_COL_REG_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DDR_MAX_ROW_REG 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DDR_MAX_ROW_REG_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* DDR0_08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DDR_DDR2_MODE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DDR_DDR2_MODE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* DDR0_10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DDR_CS_MAP 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DDR_CS_MAP_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* DDR0_14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DDR_REDUC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DDR_REDUC_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* DDR0_42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DDR_APIN 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DDR_APIN_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* DDR0_43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DDR_COL_SZ 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DDR_COL_SZ_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DDR_BANK8 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DDR_BANK8_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Some U-Boot versions set the number of chipselects to two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * for Sequoia/Rainier boards while they only have one chipselect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * hardwired. Hardcode the number of chipselects to one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * for sequioa/rainer board models or read the actual value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * from the memory controller register DDR0_10 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static inline u32 ibm4xx_denali_get_cs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) void *devp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) char model[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 val, cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) devp = finddevice("/");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!devp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) goto read_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (getprop(devp, "model", model, sizeof(model)) <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) goto read_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) model[sizeof(model)-1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (!strcmp(model, "amcc,sequoia") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) !strcmp(model, "amcc,rainier"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) read_cs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* get CS value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) val = SDRAM0_READ(DDR0_10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) cs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) while (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (val & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) cs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) val = val >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void ibm4xx_denali_fixup_memsize(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 val, max_cs, max_col, max_row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 cs, col, row, bank, dpath;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned long memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) val = SDRAM0_READ(DDR0_02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) fatal("DDR controller is not initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* get maximum cs col and row values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) cs = ibm4xx_denali_get_cs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) fatal("No memory installed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (cs > max_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) fatal("DDR wrong CS configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* get data path bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) val = SDRAM0_READ(DDR0_14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dpath = 4; /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dpath = 8; /* 64 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* get address pins (rows) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) val = SDRAM0_READ(DDR0_42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (row > max_row)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) fatal("DDR wrong APIN configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) row = max_row - row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* get collomn size and banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) val = SDRAM0_READ(DDR0_43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (col > max_col)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) fatal("DDR wrong COL configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) col = max_col - col;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (DDR_GET_VAL(val, DDR_BANK8, DDR_BANK8_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) bank = 8; /* 8 banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) bank = 4; /* 4 banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) memsize = cs * (1 << (col+row)) * bank * dpath;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) memsize = chip_11_errata(memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dt_fixup_memory(0, memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SPRN_DBCR0_40X 0x3F2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SPRN_DBCR0_44X 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DBCR0_RST_SYSTEM 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) void ibm44x_dbcr_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "mfspr %0,%1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "oris %0,%0,%2@h\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "mtspr %1,%0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) : "=&r"(tmp) : "i"(SPRN_DBCR0_44X), "i"(DBCR0_RST_SYSTEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void ibm40x_dbcr_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "mfspr %0,%1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "oris %0,%0,%2@h\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "mtspr %1,%0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) : "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define EMAC_RESET 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * do this for us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (emac0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) *emac0 = EMAC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (emac1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *emac1 = EMAC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) mtdcr(DCRN_MAL0_CFG, MAL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ; /* loop until reset takes effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Read 4xx EBC bus bridge registers to get mappings of the peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * banks into the OPB address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) void ibm4xx_fixup_ebc_ranges(const char *ebc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) void *devp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 bxcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 ranges[EBC_NUM_BANKS*4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 *p = ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) for (i = 0; i < EBC_NUM_BANKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) bxcr = mfdcr(DCRN_EBC0_CFGDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) *p++ = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) *p++ = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) *p++ = bxcr & EBC_BXCR_BAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *p++ = EBC_BXCR_BANK_SIZE(bxcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) devp = finddevice(ebc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (! devp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) fatal("Couldn't locate EBC node %s\n\r", ebc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Calculate 440GP clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 sys0 = mfdcr(DCRN_CPC0_SYS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 cr0 = mfdcr(DCRN_CPC0_CR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 opdv = CPC0_SYS0_OPDV(sys0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 epdv = CPC0_SYS0_EPDV(sys0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (sys0 & CPC0_SYS0_BYPASS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Bypass system PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) cpu = plb = sys_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (sys0 & CPC0_SYS0_EXTSL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* PerClk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* CPU clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cpu = sys_clk * m / CPC0_SYS0_FWDVA(sys0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) plb = sys_clk * m / CPC0_SYS0_FWDVB(sys0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) opb = plb / opdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ebc = opb / epdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* FIXME: Check if this is for all 440GP, or just Ebony */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if ((mfpvr() & 0xf0000fff) == 0x40000440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Rev. B 440GP, use external system clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) tb = sys_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Rev. C 440GP, errata force us to use internal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) tb = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (cr0 & CPC0_CR0_U0EC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* External UART clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) uart0 = ser_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Internal UART clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) uart0 = plb / CPC0_CR0_UDIV(cr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (cr0 & CPC0_CR0_U1EC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* External UART clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) uart1 = ser_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Internal UART clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) uart1 = plb / CPC0_CR0_UDIV(cr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) printf("PPC440GP: SysClk = %dMHz (%x)\n\r",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) (sys_clk + 500000) / 1000000, sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dt_fixup_cpu_clocks(cpu, tb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dt_fixup_clock("/plb", plb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dt_fixup_clock("/plb/opb", opb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dt_fixup_clock("/plb/opb/ebc", ebc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dt_fixup_clock("/plb/opb/serial@40000200", uart0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dt_fixup_clock("/plb/opb/serial@40000300", uart1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SPRN_CCR1 0x378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static inline u32 __fix_zero(u32 v, u32 def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return v ? v : def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static unsigned int __ibm440eplike_fixup_clocks(unsigned int sys_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned int tmr_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int per_clk_from_opb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* PLL config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 pllc = CPR0_READ(DCRN_CPR0_PLLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u32 plld = CPR0_READ(DCRN_CPR0_PLLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 fwdva = __fix_zero((plld >> 16) & 0xf, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 fwdvb = __fix_zero((plld >> 8) & 7, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 lfbdv = __fix_zero(plld & 0x3f, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 pradv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMAD) >> 24) & 7, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 prbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMBD) >> 24) & 7, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 opbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_OPBD) >> 24) & 3, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 perdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PERD) >> 24) & 3, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Input clocks for primary dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u32 clk_a, clk_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Resulting clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 cpu, plb, opb, ebc, vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Timebase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 ccr1, tb = tmr_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (pllc & 0x40000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u32 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Feedback path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) switch ((pllc >> 24) & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* PLLOUTx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) m = fwdva * pradv0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* PERClk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) m = fwdvb * prbdv0 * opbdv0 * perdv0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) printf("WARNING ! Invalid PLL feedback source !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) goto bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) m *= fbdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) vco = sys_clk * m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) clk_a = vco / fwdva;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) clk_b = vco / fwdvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) bypass:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Bypass system PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) vco = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) clk_a = clk_b = sys_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) cpu = clk_a / pradv0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) plb = clk_b / prbdv0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) opb = plb / opbdv0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ebc = (per_clk_from_opb ? opb : plb) / perdv0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Figure out timebase. Either CPU or default TmrClk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ccr1 = mfspr(SPRN_CCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* If passed a 0 tmr_clk, force CPU clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (tb == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ccr1 &= ~0x80u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) mtspr(SPRN_CCR1, ccr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if ((ccr1 & 0x0080) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) tb = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dt_fixup_cpu_clocks(cpu, tb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dt_fixup_clock("/plb", plb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dt_fixup_clock("/plb/opb", opb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dt_fixup_clock("/plb/opb/ebc", ebc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return plb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static void eplike_fixup_uart_clk(int index, const char *path,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) unsigned int ser_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned int plb_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned int sdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unsigned int clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) sdr = SDR0_READ(DCRN_SDR0_UART0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) sdr = SDR0_READ(DCRN_SDR0_UART1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) sdr = SDR0_READ(DCRN_SDR0_UART2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) sdr = SDR0_READ(DCRN_SDR0_UART3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (sdr & 0x00800000u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) clock = ser_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) clock = plb_clk / __fix_zero(sdr & 0xff, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dt_fixup_clock(path, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) void ibm440ep_fixup_clocks(unsigned int sys_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned int ser_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) unsigned int tmr_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* serial clocks need fixup based on int/ext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) eplike_fixup_uart_clk(3, "/plb/opb/serial@ef600600", ser_clk, plb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) void ibm440gx_fixup_clocks(unsigned int sys_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) unsigned int ser_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned int tmr_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* serial clocks need fixup based on int/ext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) void ibm440spe_fixup_clocks(unsigned int sys_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned int ser_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) unsigned int tmr_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* serial clocks need fixup based on int/ext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) eplike_fixup_uart_clk(0, "/plb/opb/serial@f0000200", ser_clk, plb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) eplike_fixup_uart_clk(1, "/plb/opb/serial@f0000300", ser_clk, plb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) eplike_fixup_uart_clk(2, "/plb/opb/serial@f0000600", ser_clk, plb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u32 psr = mfdcr(DCRN_405_CPC0_PSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) fbdv = (pllmr & 0x1e000000) >> 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (fbdv == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) fbdv = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ppdv = ((pllmr & 0x00006000) >> 13) + 1; /* PLB:PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* check for 405GPr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) fwdvb = 8 - (pllmr & 0x00000007);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (psr & 0x00000020) /* New mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) m = fwdvb * 2 * ppdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) m = fwdvb * cbdv * ppdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) else if (psr & 0x00000020) /* New mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (psr & 0x00000800) /* PerClk synch mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) m = fwdvb * 2 * epdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) m = fbdv * fwdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) else if (epdv == fbdv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) m = fbdv * cbdv * epdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) m = fbdv * fwdvb * cbdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) cpu = sys_clk * m / fwdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) plb = sys_clk * m / (fwdvb * cbdv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) m = fwdv * fbdv * cbdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) cpu = sys_clk * m / fwdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) plb = cpu / cbdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) opb = plb / opdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ebc = plb / epdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (cpc0_cr0 & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* uart0 uses the external clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) uart0 = ser_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) uart0 = cpu / udiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (cpc0_cr0 & 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* uart1 uses the external clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) uart1 = ser_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) uart1 = cpu / udiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* setup the timebase clock to tick at the cpu frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) cpc0_cr1 = cpc0_cr1 & ~0x00800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) tb = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) dt_fixup_cpu_clocks(cpu, tb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dt_fixup_clock("/plb", plb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dt_fixup_clock("/plb/opb", opb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dt_fixup_clock("/plb/ebc", ebc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) void ibm405ep_fixup_clocks(unsigned int sys_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u32 pllmr0 = mfdcr(DCRN_CPC0_PLLMR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u32 pllmr1 = mfdcr(DCRN_CPC0_PLLMR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u32 cpc0_ucr = mfdcr(DCRN_CPC0_UCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u32 cpu, plb, opb, ebc, uart0, uart1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u32 fwdva, fwdvb, fbdv, cbdv, opdv, epdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u32 pllmr0_ccdv, tb, m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) fwdva = 8 - ((pllmr1 & 0x00070000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) fwdvb = 8 - ((pllmr1 & 0x00007000) >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) fbdv = (pllmr1 & 0x00f00000) >> 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (fbdv == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) fbdv = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) cbdv = ((pllmr0 & 0x00030000) >> 16) + 1; /* CPU:PLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) epdv = ((pllmr0 & 0x00000300) >> 8) + 2; /* PLB:EBC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) opdv = ((pllmr0 & 0x00003000) >> 12) + 1; /* PLB:OPB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) m = fbdv * fwdvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) pllmr0_ccdv = ((pllmr0 & 0x00300000) >> 20) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (pllmr1 & 0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) cpu = sys_clk * m / (fwdva * pllmr0_ccdv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) cpu = sys_clk / pllmr0_ccdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) plb = cpu / cbdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) opb = plb / opdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ebc = plb / epdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) tb = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) uart0 = cpu / (cpc0_ucr & 0x0000007f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) uart1 = cpu / ((cpc0_ucr & 0x00007f00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dt_fixup_cpu_clocks(cpu, tb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dt_fixup_clock("/plb", plb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dt_fixup_clock("/plb/opb", opb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dt_fixup_clock("/plb/ebc", ebc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static u8 ibm405ex_fwdv_multi_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* values for: 1 - 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 0x01, 0x02, 0x0e, 0x09, 0x04, 0x0b, 0x10, 0x0d, 0x0c, 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 0x06, 0x0f, 0x0a, 0x07, 0x08, 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u32 ibm405ex_get_fwdva(unsigned long cpr_fwdv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) for (index = 0; index < ARRAY_SIZE(ibm405ex_fwdv_multi_bits); index++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (cpr_fwdv == (u32)ibm405ex_fwdv_multi_bits[index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return index + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static u8 ibm405ex_fbdv_multi_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* values for: 1 - 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 0x00, 0xff, 0x7e, 0xfd, 0x7a, 0xf5, 0x6a, 0xd5, 0x2a, 0xd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 0x29, 0xd3, 0x26, 0xcc, 0x19, 0xb3, 0x67, 0xce, 0x1d, 0xbb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 0x77, 0xee, 0x5d, 0xba, 0x74, 0xe9, 0x52, 0xa5, 0x4b, 0x96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 0x2c, 0xd8, 0x31, 0xe3, 0x46, 0x8d, 0x1b, 0xb7, 0x6f, 0xde,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 0x3d, 0xfb, 0x76, 0xed, 0x5a, 0xb5, 0x6b, 0xd6, 0x2d, 0xdb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 0x36, 0xec, 0x59, 0xb2, 0x64, 0xc9, 0x12, 0xa4, 0x48, 0x91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 0x23, 0xc7, 0x0e, 0x9c, 0x38, 0xf0, 0x61, 0xc2, 0x05, 0x8b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 0x17, 0xaf, 0x5f, 0xbe, 0x7c, 0xf9, 0x72, 0xe5, 0x4a, 0x95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 0x2b, 0xd7, 0x2e, 0xdc, 0x39, 0xf3, 0x66, 0xcd, 0x1a, 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 0x68, 0xd1, 0x22, 0xc4, 0x09, 0x93, 0x27, 0xcf, 0x1e, 0xbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* values for: 101 - 200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 0x20, 0xc0, 0x01, 0x83, 0x07, 0x8f, 0x1f, 0xbf, 0x7f, 0xfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 0x63, 0xc6, 0x0d, 0x9b, 0x37, 0xef, 0x5e, 0xbd, 0x7b, 0xf6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 0x6d, 0xda, 0x35, 0xeb, 0x56, 0xad, 0x5b, 0xb6, 0x6c, 0xd9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 0x32, 0xe4, 0x49, 0x92, 0x24, 0xc8, 0x11, 0xa3, 0x47, 0x8e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 0x1c, 0xb8, 0x70, 0xe1, 0x42, 0x85, 0x0b, 0x97, 0x2f, 0xdf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* values for: 201 - 255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 0x3e, 0xfc, 0x79, 0xf2, 0x65, 0xca, 0x15, 0xab, 0x57, 0xae,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 0x5c, 0xb9, 0x73, 0xe6, 0x4d, 0x9a, 0x34, 0xe8, 0x51, 0xa2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 0x44, 0x89, 0x13, 0xa7, 0x4f, 0x9e, 0x3c, 0xf8, 0x71, 0xe2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 0x45, 0x8a, 0x14, 0xa8, 0x50, 0xa1, 0x43, 0x86, 0x0c, 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 0x30, 0xe0, 0x41, 0x82, 0x04, 0x88, 0x10, 0xa0, 0x40, 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 0x03, 0x87, 0x0f, 0x9f, 0x3f /* END */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u32 ibm405ex_get_fbdv(unsigned long cpr_fbdv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) for (index = 0; index < ARRAY_SIZE(ibm405ex_fbdv_multi_bits); index++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (cpr_fbdv == (u32)ibm405ex_fbdv_multi_bits[index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return index + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* PLL config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u32 pllc = CPR0_READ(DCRN_CPR0_PLLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u32 plld = CPR0_READ(DCRN_CPR0_PLLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u32 cpud = CPR0_READ(DCRN_CPR0_PRIMAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u32 plbd = CPR0_READ(DCRN_CPR0_PRIMBD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u32 opbd = CPR0_READ(DCRN_CPR0_OPBD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u32 perd = CPR0_READ(DCRN_CPR0_PERD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* Dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u32 fbdv = ibm405ex_get_fbdv(__fix_zero((plld >> 24) & 0xff, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u32 fwdva = ibm405ex_get_fwdva(__fix_zero((plld >> 16) & 0x0f, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) u32 cpudv0 = __fix_zero((cpud >> 24) & 7, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* PLBDV0 is hardwared to 010. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u32 plbdv0 = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u32 plb2xdv0 = __fix_zero((plbd >> 16) & 7, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) u32 opbdv0 = __fix_zero((opbd >> 24) & 3, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u32 perdv0 = __fix_zero((perd >> 24) & 3, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Resulting clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u32 cpu, plb, opb, ebc, vco, tb, uart0, uart1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* PLL's VCO is the source for primary forward ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (pllc & 0x40000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* Feedback path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) switch ((pllc >> 24) & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* PLLOUTx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) m = fbdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) m = fbdv * fwdva * cpudv0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* PERClk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) m = fbdv * fwdva * plb2xdv0 * plbdv0 * opbdv0 * perdv0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) printf("WARNING ! Invalid PLL feedback source !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) goto bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) vco = (unsigned int)(sys_clk * m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) bypass:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Bypass system PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) vco = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* CPU = VCO / ( FWDVA x CPUDV0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) cpu = vco / (fwdva * cpudv0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* PLB = VCO / ( FWDVA x PLB2XDV0 x PLBDV0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) plb = vco / (fwdva * plb2xdv0 * plbdv0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* OPB = PLB / OPBDV0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) opb = plb / opbdv0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* EBC = OPB / PERDV0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ebc = opb / perdv0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) tb = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) uart0 = uart1 = uart_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dt_fixup_cpu_clocks(cpu, tb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dt_fixup_clock("/plb", plb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) dt_fixup_clock("/plb/opb", opb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dt_fixup_clock("/plb/opb/ebc", ebc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dt_fixup_clock("/plb/opb/serial@ef600200", uart0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dt_fixup_clock("/plb/opb/serial@ef600300", uart1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags