^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 1999 Hewlett Packard Co.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sched/debug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/extable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/hugetlb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Various important other fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define bit22set(x) (x & 0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define bits23_25set(x) (x & 0x000001c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define isGraphicsFlushRead(x) ((x & 0xfc003fdf) == 0x04001a80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* extended opcode is 0x6a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BITSSET 0x1c0 /* for identifying LDCW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int show_unhandled_signals = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * parisc_acctyp(unsigned int inst) --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Given a PA-RISC memory access instruction, determine if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * the instruction would perform a memory read or memory write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * This function assumes that the given instruction is a memory access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * instruction (i.e. you should really only call it if you know that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * the instruction has generated some sort of a memory access fault).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * VM_READ if read operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * VM_WRITE if write operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * VM_EXEC if execute operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) parisc_acctyp(unsigned long code, unsigned int inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (code == 6 || code == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return VM_EXEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) switch (inst & 0xf0000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) case 0x40000000: /* load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) case 0x50000000: /* new load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return VM_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) case 0x60000000: /* store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) case 0x70000000: /* new store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return VM_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case 0x20000000: /* coproc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case 0x30000000: /* coproc2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (bit22set(inst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return VM_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case 0x0: /* indexed/memory management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (bit22set(inst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Check for the 'Graphics Flush Read' instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * It resembles an FDC instruction, except for bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * 20 and 21. Any combination other than zero will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * utilize the block mover functionality on some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * older PA-RISC platforms. The case where a block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * move is performed from VM to graphics IO space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * should be treated as a READ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * The significance of bits 20,21 in the FDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * instruction is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * 00 Flush data cache (normal instruction behavior)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * 01 Graphics flush write (IO space -> VM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * 10 Graphics flush read (VM -> IO space)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * 11 Graphics flush read/write (VM <-> IO space)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (isGraphicsFlushRead(inst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return VM_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return VM_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * Check for LDCWX and LDCWS (semaphore instructions).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * If bits 23 through 25 are all 1's it is one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * the above two instructions and is a write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Note: With the limited bits we are looking at,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * this will also catch PROBEW and PROBEWI. However,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * these should never get in here because they don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * generate exceptions of the type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Data TLB miss fault/data page fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Data memory protection trap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (bits23_25set(inst) == BITSSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return VM_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return VM_READ; /* Default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return VM_READ; /* Default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #undef bit22set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #undef bits23_25set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #undef isGraphicsFlushRead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #undef BITSSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* This is the treewalk to find a vma which is the highest that has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * a start < addr. We're using find_vma_prev instead right now, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * we might want to use this at some point in the future. Probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * not, but I want it committed to CVS so I don't lose it :-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) while (tree != vm_avl_empty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (tree->vm_start > addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) tree = tree->vm_avl_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) prev = tree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (prev->vm_next == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (prev->vm_next->vm_start > addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) tree = tree->vm_avl_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int fixup_exception(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const struct exception_table_entry *fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) fix = search_exception_tables(regs->iaoq[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (fix) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Fix up get_user() and put_user().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * ASM_EXCEPTIONTABLE_ENTRY_EFAULT() sets the least-significant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * bit in the relative address of the fixup routine to indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * that %r8 should be loaded with -EFAULT to report a userspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * access error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (fix->fixup & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) regs->gr[8] = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* zero target register for get_user() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (parisc_acctyp(0, regs->iir) == VM_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int treg = regs->iir & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) BUG_ON(treg == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) regs->gr[treg] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) regs->iaoq[0] = (unsigned long)&fix->fixup + fix->fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) regs->iaoq[0] &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * NOTE: In some cases the faulting instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * may be in the delay slot of a branch. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * don't want to take the branch, so we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * increment iaoq[1], instead we set it to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * iaoq[0]+4, and clear the B bit in the PSW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) regs->iaoq[1] = regs->iaoq[0] + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * parisc hardware trap list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Documented in section 3 "Addressing and Access Control" of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * "PA-RISC 1.1 Architecture and Instruction Set Reference Manual"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * https://parisc.wiki.kernel.org/index.php/File:Pa11_acd.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * For implementation see handle_interruption() in traps.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const char * const trap_description[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [1] "High-priority machine check (HPMC)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [2] "Power failure interrupt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) [3] "Recovery counter trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) [5] "Low-priority machine check",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) [6] "Instruction TLB miss fault",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) [7] "Instruction access rights / protection trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [8] "Illegal instruction trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) [9] "Break instruction trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) [10] "Privileged operation trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) [11] "Privileged register trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) [12] "Overflow trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) [13] "Conditional trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) [14] "FP Assist Exception trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) [15] "Data TLB miss fault",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) [16] "Non-access ITLB miss fault",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) [17] "Non-access DTLB miss fault",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [18] "Data memory protection/unaligned access trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) [19] "Data memory break trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) [20] "TLB dirty bit trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) [21] "Page reference trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) [22] "Assist emulation trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [25] "Taken branch trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [26] "Data memory access rights trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) [27] "Data memory protection ID trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) [28] "Unaligned data reference trap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) const char *trap_name(unsigned long code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) const char *t = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (code < ARRAY_SIZE(trap_description))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) t = trap_description[code];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return t ? t : "Unknown trap";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Print out info about fatal segfaults, if the show_unhandled_signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * sysctl is set:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) show_signal_msg(struct pt_regs *regs, unsigned long code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned long address, struct task_struct *tsk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (!unhandled_signal(tsk, SIGSEGV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!printk_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) pr_warn("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) pr_warn("do_page_fault() command='%s' type=%lu address=0x%08lx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tsk->comm, code, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) print_vma_addr(KERN_CONT " in ", regs->iaoq[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pr_cont("\ntrap #%lu: %s%c", code, trap_name(code),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) vma ? ',':'\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pr_cont(" vm_start = 0x%08lx, vm_end = 0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) vma->vm_start, vma->vm_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) show_regs(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) void do_page_fault(struct pt_regs *regs, unsigned long code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned long address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct vm_area_struct *vma, *prev_vma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct task_struct *tsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct mm_struct *mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned long acc_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) vm_fault_t fault = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (faulthandler_disabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) goto no_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) tsk = current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mm = tsk->mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) goto no_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) flags = FAULT_FLAG_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (user_mode(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) flags |= FAULT_FLAG_USER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) acc_type = parisc_acctyp(code, regs->iir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (acc_type & VM_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) flags |= FAULT_FLAG_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) mmap_read_lock(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) vma = find_vma_prev(mm, address, &prev_vma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (!vma || address < vma->vm_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) goto check_expansion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * Ok, we have a good vm_area for this memory access. We still need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * check the access permissions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) good_area:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if ((vma->vm_flags & acc_type) != acc_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) goto bad_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * If for any reason at all we couldn't handle the fault, make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * sure we exit gracefully rather than endlessly redo the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * fault.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) fault = handle_mm_fault(vma, address, flags, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (fault_signal_pending(fault, regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (unlikely(fault & VM_FAULT_ERROR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * We hit a shared mapping outside of the file, or some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * other thing happened to us that made us unable to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * handle the page fault gracefully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (fault & VM_FAULT_OOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) goto out_of_memory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) else if (fault & VM_FAULT_SIGSEGV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) goto bad_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) else if (fault & (VM_FAULT_SIGBUS|VM_FAULT_HWPOISON|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) VM_FAULT_HWPOISON_LARGE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) goto bad_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (flags & FAULT_FLAG_ALLOW_RETRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (fault & VM_FAULT_RETRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * No need to mmap_read_unlock(mm) as we would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * have already released it in __lock_page_or_retry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * in mm/filemap.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) flags |= FAULT_FLAG_TRIED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mmap_read_unlock(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) check_expansion:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) vma = prev_vma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (vma && (expand_stack(vma, address) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) goto good_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Something tried to access memory that isn't in our memory map..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) bad_area:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mmap_read_unlock(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (user_mode(regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int signo, si_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) switch (code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case 15: /* Data TLB miss fault/Data page fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* send SIGSEGV when outside of vma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (!vma ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) address < vma->vm_start || address >= vma->vm_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) signo = SIGSEGV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) si_code = SEGV_MAPERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* send SIGSEGV for wrong permissions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if ((vma->vm_flags & acc_type) != acc_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) signo = SIGSEGV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) si_code = SEGV_ACCERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* probably address is outside of mapped file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case 17: /* NA data TLB miss / page fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case 18: /* Unaligned access - PCXS only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) signo = SIGBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) si_code = (code == 18) ? BUS_ADRALN : BUS_ADRERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case 16: /* Non-access instruction TLB miss fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case 26: /* PCXL: Data memory access rights trap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) signo = SIGSEGV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #ifdef CONFIG_MEMORY_FAILURE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (fault & (VM_FAULT_HWPOISON|VM_FAULT_HWPOISON_LARGE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int lsb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "MCE: Killing %s:%d due to hardware memory corruption fault at %08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) tsk->comm, tsk->pid, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * Either small page or large page may be poisoned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * In other words, VM_FAULT_HWPOISON_LARGE and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * VM_FAULT_HWPOISON are mutually exclusive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (fault & VM_FAULT_HWPOISON_LARGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) else if (fault & VM_FAULT_HWPOISON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) lsb = PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) force_sig_mceerr(BUS_MCEERR_AR, (void __user *) address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) show_signal_msg(regs, code, address, tsk, vma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) force_sig_fault(signo, si_code, (void __user *) address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) no_context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!user_mode(regs) && fixup_exception(regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) parisc_terminate("Bad Address (null pointer deref?)", regs, code, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) out_of_memory:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) mmap_read_unlock(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!user_mode(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) goto no_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pagefault_out_of_memory();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* Handle non-access data TLB miss faults.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * For probe instructions, accesses to userspace are considered allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * if they lie in a valid VMA and the access type matches. We are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * allowed to handle MM faults here so there may be situations where an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * actual access would fail even though a probe was successful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) handle_nadtlb_fault(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned long insn = regs->iir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int breg, treg, xreg, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct vm_area_struct *vma, *prev_vma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct task_struct *tsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct mm_struct *mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned long address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned long acc_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) switch (insn & 0x380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case 0x280:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* FDC instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case 0x380:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* PDC and FIC instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (printk_ratelimit()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pr_warn("BUG: nullifying cache flush/purge instruction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) show_regs(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (insn & 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Base modification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) breg = (insn >> 21) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) xreg = (insn >> 16) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (breg && xreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) regs->gr[breg] += regs->gr[xreg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) regs->gr[0] |= PSW_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case 0x180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* PROBE instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) treg = insn & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (regs->isr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) tsk = current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) mm = tsk->mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (mm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Search for VMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) address = regs->ior;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mmap_read_lock(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) vma = find_vma_prev(mm, address, &prev_vma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) mmap_read_unlock(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * Check if access to the VMA is okay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * We don't allow for stack expansion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) acc_type = (insn & 0x40) ? VM_WRITE : VM_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (vma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) && address >= vma->vm_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) && (vma->vm_flags & acc_type) == acc_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (treg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) regs->gr[treg] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) regs->gr[0] |= PSW_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case 0x300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* LPA instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (insn & 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Base modification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) breg = (insn >> 21) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) xreg = (insn >> 16) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (breg && xreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) regs->gr[breg] += regs->gr[xreg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) treg = insn & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (treg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) regs->gr[treg] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) regs->gr[0] |= PSW_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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