^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Linux/PA-RISC Project (http://www.parisc-linux.org/)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Floating-point emulation code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * BEGIN_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * File:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * @(#) pa/fp/fpudispatch.c $Revision: 1.1 $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Purpose:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * <<please update with a synopsis of the functionality provided by this file>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * External Interfaces:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * <<the following list was autogenerated, please review>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * emfpudispatch(ir, dummy1, dummy2, fpregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * fpudispatch(ir, excp_code, holder, fpregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Internal Interfaces:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * <<the following list was autogenerated, please review>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * static u_int decode_06(u_int, u_int *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * static u_int decode_0c(u_int, u_int, u_int, u_int *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * static u_int decode_0e(u_int, u_int, u_int, u_int *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * static u_int decode_26(u_int, u_int *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * static u_int decode_2e(u_int, u_int *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * static void update_status_cbit(u_int *, u_int, u_int, u_int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Theory:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * <<please update with a overview of the operation of this file>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * END_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FPUDEBUG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "float.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* #include <sys/debug.h> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* #include <machine/sys/mdep_private.h> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define COPR_INST 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * definition of extru macro. If pos and len are constants, the compiler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * will generate an extru instruction when optimized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define extru(r,pos,len) (((r) >> (31-(pos))) & (( 1 << (len)) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* definitions of bit field locations in the instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define fpmajorpos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define fpr1pos 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define fpr2pos 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define fptpos 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define fpsubpos 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define fpclass1subpos 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define fpclasspos 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define fpfmtpos 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define fpdfpos 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define fpnulpos 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * the following are the extra bits for the 0E major op
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define fpxr1pos 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define fpxr2pos 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define fpxtpos 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define fpxpos 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define fp0efmtpos 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * the following are for the multi-ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define fprm1pos 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define fprm2pos 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define fptmpos 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define fprapos 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define fptapos 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define fpmultifmt 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * the following are for the fused FP instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* fprm1pos 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* fprm2pos 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define fpraupos 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define fpxrm2pos 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* fpfmtpos 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define fpralpos 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define fpxrm1pos 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* fpxtpos 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define fpfusedsubop 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* fptpos 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * offset to constant zero in the FP emulation registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define fpzeroreg (32*sizeof(double)/sizeof(u_int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * extract the major opcode from the instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define get_major(op) extru(op,fpmajorpos,6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * extract the two bit class field from the FP instruction. The class is at bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * positions 21-22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define get_class(op) extru(op,fpclasspos,2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * extract the 3 bit subop field. For all but class 1 instructions, it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * located at bit positions 16-18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define get_subop(op) extru(op,fpsubpos,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * extract the 2 or 3 bit subop field from class 1 instructions. It is located
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * at bit positions 15-16 (PA1.1) or 14-16 (PA2.0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define get_subop1_PA1_1(op) extru(op,fpclass1subpos,2) /* PA89 (1.1) fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define get_subop1_PA2_0(op) extru(op,fpclass1subpos,3) /* PA 2.0 fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* definitions of unimplemented exceptions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MAJOR_0C_EXCP 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MAJOR_0E_EXCP 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MAJOR_06_EXCP 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MAJOR_26_EXCP 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MAJOR_2E_EXCP 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PA83_UNIMP_EXCP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Special Defines for TIMEX specific code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define FPU_TYPE_FLAG_POS (EM_FPU_TYPE_OFFSET>>2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TIMEX_ROLEX_FPU_MASK (TIMEX_EXTEN_FLAG|ROLEX_EXTEN_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * Static function definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define _PROTOTYPES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #if defined(_PROTOTYPES) || defined(_lint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static u_int decode_0c(u_int, u_int, u_int, u_int *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static u_int decode_0e(u_int, u_int, u_int, u_int *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static u_int decode_06(u_int, u_int *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static u_int decode_26(u_int, u_int *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static u_int decode_2e(u_int, u_int *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void update_status_cbit(u_int *, u_int, u_int, u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #else /* !_PROTOTYPES&&!_lint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static u_int decode_0c();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static u_int decode_0e();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static u_int decode_06();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static u_int decode_26();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static u_int decode_2e();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void update_status_cbit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #endif /* _PROTOTYPES&&!_lint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define VASSERT(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void parisc_linux_get_fpu_type(u_int fpregs[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* on pa-linux the fpu type is not filled in by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * caller; it is constructed here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (boot_cpu_data.cpu_type == pcxs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) fpregs[FPU_TYPE_FLAG_POS] = TIMEX_EXTEN_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) else if (boot_cpu_data.cpu_type == pcxt ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) boot_cpu_data.cpu_type == pcxt_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) fpregs[FPU_TYPE_FLAG_POS] = ROLEX_EXTEN_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) else if (boot_cpu_data.cpu_type >= pcxu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) fpregs[FPU_TYPE_FLAG_POS] = PA2_0_FPU_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * this routine will decode the excepting floating point instruction and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * call the appropriate emulation routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * It is called by decode_fpu with the following parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * fpudispatch(current_ir, unimplemented_code, 0, &Fpu_register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * where current_ir is the instruction to be emulated,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * unimplemented_code is the exception_code that the hardware generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * and &Fpu_register is the address of emulated FP reg 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u_int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) fpudispatch(u_int ir, u_int excp_code, u_int holder, u_int fpregs[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u_int class, subop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u_int fpu_type_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* All FP emulation code assumes that ints are 4-bytes in length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) VASSERT(sizeof(int) == 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) parisc_linux_get_fpu_type(fpregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) fpu_type_flags=fpregs[FPU_TYPE_FLAG_POS]; /* get fpu type flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) class = get_class(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (class == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (fpu_type_flags & PA2_0_FPU_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) subop = get_subop1_PA2_0(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) subop = get_subop1_PA1_1(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) subop = get_subop(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (FPUDEBUG) printk("class %d subop %d\n", class, subop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) switch (excp_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case MAJOR_0C_EXCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case PA83_UNIMP_EXCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return(decode_0c(ir,class,subop,fpregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case MAJOR_0E_EXCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return(decode_0e(ir,class,subop,fpregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case MAJOR_06_EXCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return(decode_06(ir,fpregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) case MAJOR_26_EXCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return(decode_26(ir,fpregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case MAJOR_2E_EXCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return(decode_2e(ir,fpregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* "crashme Night Gallery painting nr 2. (asm_crash.s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * This was fixed for multi-user kernels, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * workstation kernels had a panic here. This allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * any arbitrary user to panic the kernel by executing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * setting the FP exception registers to strange values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * and generating an emulation trap. The emulation and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * exception code must never be able to panic the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return(UNIMPLEMENTEDEXCEPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * this routine is called by $emulation_trap to emulate a coprocessor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * instruction if one doesn't exist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u_int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) emfpudispatch(u_int ir, u_int dummy1, u_int dummy2, u_int fpregs[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u_int class, subop, major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u_int fpu_type_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* All FP emulation code assumes that ints are 4-bytes in length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) VASSERT(sizeof(int) == 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) fpu_type_flags=fpregs[FPU_TYPE_FLAG_POS]; /* get fpu type flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) major = get_major(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) class = get_class(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (class == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (fpu_type_flags & PA2_0_FPU_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) subop = get_subop1_PA2_0(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) subop = get_subop1_PA1_1(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) subop = get_subop(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) switch (major) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case 0x0C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return(decode_0c(ir,class,subop,fpregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case 0x0E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return(decode_0e(ir,class,subop,fpregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case 0x06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return(decode_06(ir,fpregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case 0x26:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return(decode_26(ir,fpregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case 0x2E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return(decode_2e(ir,fpregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return(PA83_UNIMP_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static u_int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u_int r1,r2,t; /* operand register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u_int fmt; /* also sf for class 1 conversions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u_int df; /* for class 1 conversions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u_int *status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u_int retval, local_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u_int fpu_type_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (ir == COPR_INST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) fpregs[0] = EMULATION_VERSION << 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return(NOEXCEPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) status = &fpregs[0]; /* fp status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) local_status = fpregs[0]; /* and local copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) r1 = extru(ir,fpr1pos,5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (r1 == 0) /* map fr0 source to constant zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) r1 = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) t = extru(ir,fptpos,5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (t == 0 && class != 2) /* don't allow fr0 as a dest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) fmt = extru(ir,fpfmtpos,2); /* get fmt completer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) switch (class) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) switch (subop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case 0: /* COPR 0,0 emulated above*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case 2: /* FCPY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case 2: /* illegal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case 3: /* quad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) t &= ~3; /* force to even reg #s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) r1 &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) fpregs[t+3] = fpregs[r1+3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) fpregs[t+2] = fpregs[r1+2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case 1: /* double */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) fpregs[t+1] = fpregs[r1+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case 0: /* single */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) fpregs[t] = fpregs[r1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return(NOEXCEPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case 3: /* FABS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) case 2: /* illegal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case 3: /* quad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) t &= ~3; /* force to even reg #s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) r1 &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) fpregs[t+3] = fpregs[r1+3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) fpregs[t+2] = fpregs[r1+2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case 1: /* double */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) fpregs[t+1] = fpregs[r1+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case 0: /* single */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* copy and clear sign bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) fpregs[t] = fpregs[r1] & 0x7fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return(NOEXCEPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case 6: /* FNEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) case 2: /* illegal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case 3: /* quad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) t &= ~3; /* force to even reg #s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) r1 &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) fpregs[t+3] = fpregs[r1+3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) fpregs[t+2] = fpregs[r1+2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case 1: /* double */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) fpregs[t+1] = fpregs[r1+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case 0: /* single */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* copy and invert sign bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) fpregs[t] = fpregs[r1] ^ 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return(NOEXCEPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case 7: /* FNEGABS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case 2: /* illegal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case 3: /* quad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) t &= ~3; /* force to even reg #s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) r1 &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) fpregs[t+3] = fpregs[r1+3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) fpregs[t+2] = fpregs[r1+2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) case 1: /* double */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) fpregs[t+1] = fpregs[r1+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case 0: /* single */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* copy and set sign bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) fpregs[t] = fpregs[r1] | 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return(NOEXCEPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case 4: /* FSQRT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return(sgl_fsqrt(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return(dbl_fsqrt(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case 3: /* quad not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case 5: /* FRND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return(sgl_frnd(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return(dbl_frnd(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case 3: /* quad not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) } /* end of switch (subop) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case 1: /* class 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) df = extru(ir,fpdfpos,2); /* get dest format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if ((df & 2) || (fmt & 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * fmt's 2 and 3 are illegal of not implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * quad conversions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * encode source and dest formats into 2 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * high bit is source, low bit is dest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * bit = 1 --> double precision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) fmt = (fmt << 1) | df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) switch (subop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) case 0: /* FCNVFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) switch(fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case 0: /* sgl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case 1: /* sgl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return(sgl_to_dbl_fcnvff(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case 2: /* dbl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return(dbl_to_sgl_fcnvff(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case 3: /* dbl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case 1: /* FCNVXF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) switch(fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case 0: /* sgl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return(sgl_to_sgl_fcnvxf(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case 1: /* sgl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return(sgl_to_dbl_fcnvxf(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case 2: /* dbl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return(dbl_to_sgl_fcnvxf(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case 3: /* dbl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return(dbl_to_dbl_fcnvxf(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case 2: /* FCNVFX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) switch(fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case 0: /* sgl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return(sgl_to_sgl_fcnvfx(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case 1: /* sgl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return(sgl_to_dbl_fcnvfx(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case 2: /* dbl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return(dbl_to_sgl_fcnvfx(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case 3: /* dbl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return(dbl_to_dbl_fcnvfx(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case 3: /* FCNVFXT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) switch(fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case 0: /* sgl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return(sgl_to_sgl_fcnvfxt(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case 1: /* sgl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return(sgl_to_dbl_fcnvfxt(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case 2: /* dbl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return(dbl_to_sgl_fcnvfxt(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case 3: /* dbl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return(dbl_to_dbl_fcnvfxt(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case 5: /* FCNVUF (PA2.0 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) switch(fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case 0: /* sgl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return(sgl_to_sgl_fcnvuf(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case 1: /* sgl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return(sgl_to_dbl_fcnvuf(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case 2: /* dbl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return(dbl_to_sgl_fcnvuf(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case 3: /* dbl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return(dbl_to_dbl_fcnvuf(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) case 6: /* FCNVFU (PA2.0 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) switch(fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case 0: /* sgl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return(sgl_to_sgl_fcnvfu(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) case 1: /* sgl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return(sgl_to_dbl_fcnvfu(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case 2: /* dbl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return(dbl_to_sgl_fcnvfu(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) case 3: /* dbl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return(dbl_to_dbl_fcnvfu(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case 7: /* FCNVFUT (PA2.0 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) switch(fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) case 0: /* sgl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return(sgl_to_sgl_fcnvfut(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) case 1: /* sgl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return(sgl_to_dbl_fcnvfut(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) case 2: /* dbl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return(dbl_to_sgl_fcnvfut(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case 3: /* dbl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return(dbl_to_dbl_fcnvfut(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case 4: /* undefined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) } /* end of switch subop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case 2: /* class 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) fpu_type_flags=fpregs[FPU_TYPE_FLAG_POS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) r2 = extru(ir, fpr2pos, 5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (r2 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) r2 = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (fpu_type_flags & PA2_0_FPU_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* FTEST if nullify bit set, otherwise FCMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (extru(ir, fpnulpos, 1)) { /* FTEST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * arg0 is not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * second param is the t field used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * ftest,acc and ftest,rej
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * third param is the subop (y-field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Unsupported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * return(ftest(0L,extru(ir,fptpos,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * &fpregs[0],subop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) } else { /* FCMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) retval = sgl_fcmp(&fpregs[r1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) &fpregs[r2],extru(ir,fptpos,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) &local_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) update_status_cbit(status,local_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) fpu_type_flags, subop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return(retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) retval = dbl_fcmp(&fpregs[r1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) &fpregs[r2],extru(ir,fptpos,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) &local_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) update_status_cbit(status,local_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) fpu_type_flags, subop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return(retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case 2: /* illegal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case 3: /* quad not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) } /* end of if for PA2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) else { /* PA1.0 & PA1.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) switch (subop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case 0: /* FCMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) retval = sgl_fcmp(&fpregs[r1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) &fpregs[r2],extru(ir,fptpos,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) &local_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) update_status_cbit(status,local_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) fpu_type_flags, subop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return(retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) retval = dbl_fcmp(&fpregs[r1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) &fpregs[r2],extru(ir,fptpos,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) &local_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) update_status_cbit(status,local_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) fpu_type_flags, subop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return(retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) case 2: /* illegal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) case 3: /* quad not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case 1: /* FTEST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * arg0 is not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * second param is the t field used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * ftest,acc and ftest,rej
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * third param is the subop (y-field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* unsupported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * return(ftest(0L,extru(ir,fptpos,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * &fpregs[0],subop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) } /* end of switch subop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) } /* end of else for PA1.0 & PA1.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) case 3: /* class 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) r2 = extru(ir,fpr2pos,5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (r2 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) r2 = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) switch (subop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case 0: /* FADD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return(sgl_fadd(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return(dbl_fadd(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) case 2: /* illegal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) case 3: /* quad not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) case 1: /* FSUB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return(sgl_fsub(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return(dbl_fsub(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) case 2: /* illegal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) case 3: /* quad not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) case 2: /* FMPY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return(sgl_fmpy(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return(dbl_fmpy(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) case 2: /* illegal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) case 3: /* quad not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) case 3: /* FDIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return(sgl_fdiv(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return(dbl_fdiv(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) case 2: /* illegal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) case 3: /* quad not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) case 4: /* FREM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return(sgl_frem(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return(dbl_frem(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) case 2: /* illegal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) case 3: /* quad not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) } /* end of class 3 switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) } /* end of switch(class) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* If we get here, something is really wrong! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static u_int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) decode_0e(ir,class,subop,fpregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) u_int ir,class,subop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u_int fpregs[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u_int r1,r2,t; /* operand register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u_int fmt; /* also sf for class 1 conversions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u_int df; /* dest format for class 1 conversions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u_int *status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u_int retval, local_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u_int fpu_type_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) status = &fpregs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) local_status = fpregs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) r1 = ((extru(ir,fpr1pos,5)<<1)|(extru(ir,fpxr1pos,1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (r1 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) r1 = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) t = ((extru(ir,fptpos,5)<<1)|(extru(ir,fpxtpos,1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (t == 0 && class != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (class < 2) /* class 0 or 1 has 2 bit fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) fmt = extru(ir,fpfmtpos,2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) else /* class 2 and 3 have 1 bit fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) fmt = extru(ir,fp0efmtpos,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * An undefined combination, double precision accessing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * right half of a FPR, can get us into trouble.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * Let's just force proper alignment on it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (fmt == DBL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) r1 &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (class != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) t &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) switch (class) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) switch (subop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) case 0: /* unimplemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case 2: /* FCPY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) case 1: /* double */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) fpregs[t+1] = fpregs[r1+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) case 0: /* single */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) fpregs[t] = fpregs[r1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return(NOEXCEPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) case 3: /* FABS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) case 1: /* double */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) fpregs[t+1] = fpregs[r1+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) case 0: /* single */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) fpregs[t] = fpregs[r1] & 0x7fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return(NOEXCEPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) case 6: /* FNEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) case 1: /* double */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) fpregs[t+1] = fpregs[r1+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) case 0: /* single */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) fpregs[t] = fpregs[r1] ^ 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return(NOEXCEPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) case 7: /* FNEGABS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) case 1: /* double */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) fpregs[t+1] = fpregs[r1+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case 0: /* single */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) fpregs[t] = fpregs[r1] | 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return(NOEXCEPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) case 4: /* FSQRT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return(sgl_fsqrt(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) &fpregs[t], status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return(dbl_fsqrt(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) &fpregs[t], status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) case 5: /* FRMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return(sgl_frnd(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) &fpregs[t], status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return(dbl_frnd(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) &fpregs[t], status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) } /* end of switch (subop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) case 1: /* class 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) df = extru(ir,fpdfpos,2); /* get dest format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * Fix Crashme problem (writing to 31R in double precision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * here too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (df == DBL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) t &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if ((df & 2) || (fmt & 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) fmt = (fmt << 1) | df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) switch (subop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) case 0: /* FCNVFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) switch(fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) case 0: /* sgl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) case 1: /* sgl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return(sgl_to_dbl_fcnvff(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) case 2: /* dbl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return(dbl_to_sgl_fcnvff(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) case 3: /* dbl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) case 1: /* FCNVXF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) switch(fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) case 0: /* sgl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return(sgl_to_sgl_fcnvxf(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) case 1: /* sgl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return(sgl_to_dbl_fcnvxf(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) case 2: /* dbl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return(dbl_to_sgl_fcnvxf(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) case 3: /* dbl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return(dbl_to_dbl_fcnvxf(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) case 2: /* FCNVFX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) switch(fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) case 0: /* sgl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return(sgl_to_sgl_fcnvfx(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) case 1: /* sgl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return(sgl_to_dbl_fcnvfx(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) case 2: /* dbl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return(dbl_to_sgl_fcnvfx(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) case 3: /* dbl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return(dbl_to_dbl_fcnvfx(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case 3: /* FCNVFXT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) switch(fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) case 0: /* sgl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return(sgl_to_sgl_fcnvfxt(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) case 1: /* sgl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return(sgl_to_dbl_fcnvfxt(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case 2: /* dbl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return(dbl_to_sgl_fcnvfxt(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) case 3: /* dbl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return(dbl_to_dbl_fcnvfxt(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case 5: /* FCNVUF (PA2.0 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) switch(fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) case 0: /* sgl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return(sgl_to_sgl_fcnvuf(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) case 1: /* sgl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return(sgl_to_dbl_fcnvuf(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) case 2: /* dbl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return(dbl_to_sgl_fcnvuf(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) case 3: /* dbl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return(dbl_to_dbl_fcnvuf(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) case 6: /* FCNVFU (PA2.0 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) switch(fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) case 0: /* sgl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return(sgl_to_sgl_fcnvfu(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) case 1: /* sgl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return(sgl_to_dbl_fcnvfu(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) case 2: /* dbl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return(dbl_to_sgl_fcnvfu(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) case 3: /* dbl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return(dbl_to_dbl_fcnvfu(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) case 7: /* FCNVFUT (PA2.0 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) switch(fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) case 0: /* sgl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return(sgl_to_sgl_fcnvfut(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) case 1: /* sgl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return(sgl_to_dbl_fcnvfut(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) case 2: /* dbl/sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return(dbl_to_sgl_fcnvfut(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) case 3: /* dbl/dbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return(dbl_to_dbl_fcnvfut(&fpregs[r1],0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) case 4: /* undefined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return(MAJOR_0C_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) } /* end of switch subop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) case 2: /* class 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * Be careful out there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * Crashme can generate cases where FR31R is specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * as the source or target of a double precision operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * Since we just pass the address of the floating-point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * register to the emulation routines, this can cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * corruption of fpzeroreg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (fmt == DBL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) r2 = (extru(ir,fpr2pos,5)<<1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) r2 = ((extru(ir,fpr2pos,5)<<1)|(extru(ir,fpxr2pos,1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) fpu_type_flags=fpregs[FPU_TYPE_FLAG_POS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (r2 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) r2 = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (fpu_type_flags & PA2_0_FPU_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /* FTEST if nullify bit set, otherwise FCMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (extru(ir, fpnulpos, 1)) { /* FTEST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* not legal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) } else { /* FCMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * fmt is only 1 bit long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) retval = sgl_fcmp(&fpregs[r1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) &fpregs[r2],extru(ir,fptpos,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) &local_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) update_status_cbit(status,local_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) fpu_type_flags, subop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return(retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) retval = dbl_fcmp(&fpregs[r1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) &fpregs[r2],extru(ir,fptpos,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) &local_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) update_status_cbit(status,local_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) fpu_type_flags, subop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return(retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) } /* end of if for PA2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) else { /* PA1.0 & PA1.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) switch (subop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) case 0: /* FCMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * fmt is only 1 bit long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) retval = sgl_fcmp(&fpregs[r1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) &fpregs[r2],extru(ir,fptpos,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) &local_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) update_status_cbit(status,local_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) fpu_type_flags, subop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return(retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) retval = dbl_fcmp(&fpregs[r1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) &fpregs[r2],extru(ir,fptpos,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) &local_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) update_status_cbit(status,local_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) fpu_type_flags, subop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return(retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) } /* end of switch subop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) } /* end of else for PA1.0 & PA1.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) case 3: /* class 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * Be careful out there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * Crashme can generate cases where FR31R is specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * as the source or target of a double precision operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * Since we just pass the address of the floating-point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * register to the emulation routines, this can cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * corruption of fpzeroreg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (fmt == DBL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) r2 = (extru(ir,fpr2pos,5)<<1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) r2 = ((extru(ir,fpr2pos,5)<<1)|(extru(ir,fpxr2pos,1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (r2 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) r2 = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) switch (subop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * Note that fmt is only 1 bit for class 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) case 0: /* FADD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return(sgl_fadd(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return(dbl_fadd(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) case 1: /* FSUB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return(sgl_fsub(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return(dbl_fsub(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) case 2: /* FMPY or XMPYU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * check for integer multiply (x bit set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (extru(ir,fpxpos,1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * emulate XMPYU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * bad instruction if t specifies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * the right half of a register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (t & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* unsupported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * impyu(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * &fpregs[t]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return(NOEXCEPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) else { /* FMPY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return(sgl_fmpy(&fpregs[r1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) &fpregs[r2],&fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return(dbl_fmpy(&fpregs[r1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) &fpregs[r2],&fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) case 3: /* FDIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return(sgl_fdiv(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return(dbl_fdiv(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) case 4: /* FREM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return(sgl_frem(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return(dbl_frem(&fpregs[r1],&fpregs[r2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) &fpregs[t],status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) } /* end of class 3 switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) } /* end of switch(class) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* If we get here, something is really wrong! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return(MAJOR_0E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * routine to decode the 06 (FMPYADD and FMPYCFXT) instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static u_int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) decode_06(ir,fpregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) u_int ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) u_int fpregs[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) u_int rm1, rm2, tm, ra, ta; /* operands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) u_int fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) u_int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) u_int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) u_int fpu_type_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) double dbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) float flt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct { u_int i1; u_int i2; } ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) } mtmp, atmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) status = fpregs[0]; /* use a local copy of status reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) fpu_type_flags=fpregs[FPU_TYPE_FLAG_POS]; /* get fpu type flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) fmt = extru(ir, fpmultifmt, 1); /* get sgl/dbl flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (fmt == 0) { /* DBL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) rm1 = extru(ir, fprm1pos, 5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (rm1 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) rm1 = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) rm2 = extru(ir, fprm2pos, 5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (rm2 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) rm2 = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) tm = extru(ir, fptmpos, 5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (tm == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return(MAJOR_06_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ra = extru(ir, fprapos, 5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ta = extru(ir, fptapos, 5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (ta == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return(MAJOR_06_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (fpu_type_flags & TIMEX_ROLEX_FPU_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (ra == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /* special case FMPYCFXT, see sgl case below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) &mtmp.ints.i1,&status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (dbl_to_sgl_fcnvfxt(&fpregs[ta],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) &atmp.ints.i1,&atmp.ints.i1,&status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) &status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (dbl_fadd(&fpregs[ta], &fpregs[ra], &atmp.ints.i1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) &status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (ra == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ra = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) &status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (dbl_fadd(&fpregs[ta], &fpregs[ra], &atmp.ints.i1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) &status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return(MAJOR_06_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /* copy results */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) fpregs[tm] = mtmp.ints.i1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) fpregs[tm+1] = mtmp.ints.i2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) fpregs[ta] = atmp.ints.i1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) fpregs[ta+1] = atmp.ints.i2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) fpregs[0] = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return(NOEXCEPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) else { /* SGL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * calculate offsets for single precision numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * See table 6-14 in PA-89 architecture for mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) rm1 = (extru(ir,fprm1pos,4) | 0x10 ) << 1; /* get offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) rm1 |= extru(ir,fprm1pos-4,1); /* add right word offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) rm2 = (extru(ir,fprm2pos,4) | 0x10 ) << 1; /* get offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) rm2 |= extru(ir,fprm2pos-4,1); /* add right word offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) tm = (extru(ir,fptmpos,4) | 0x10 ) << 1; /* get offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) tm |= extru(ir,fptmpos-4,1); /* add right word offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) ra = (extru(ir,fprapos,4) | 0x10 ) << 1; /* get offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) ra |= extru(ir,fprapos-4,1); /* add right word offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ta = (extru(ir,fptapos,4) | 0x10 ) << 1; /* get offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ta |= extru(ir,fptapos-4,1); /* add right word offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (ra == 0x20 &&(fpu_type_flags & TIMEX_ROLEX_FPU_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* special case FMPYCFXT (really 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * This instruction is only present on the Timex and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * Rolex fpu's in so if it is the special case and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * one of these fpu's we run the FMPYCFXT instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (sgl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) &status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (sgl_to_sgl_fcnvfxt(&fpregs[ta],&atmp.ints.i1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) &atmp.ints.i1,&status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (sgl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) &status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (sgl_fadd(&fpregs[ta], &fpregs[ra], &atmp.ints.i1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) &status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return(MAJOR_06_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* copy results */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) fpregs[tm] = mtmp.ints.i1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) fpregs[ta] = atmp.ints.i1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) fpregs[0] = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return(NOEXCEPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * routine to decode the 26 (FMPYSUB) instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) static u_int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) decode_26(ir,fpregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) u_int ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) u_int fpregs[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) u_int rm1, rm2, tm, ra, ta; /* operands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) u_int fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) u_int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) u_int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) double dbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) float flt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct { u_int i1; u_int i2; } ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) } mtmp, atmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) status = fpregs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) fmt = extru(ir, fpmultifmt, 1); /* get sgl/dbl flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (fmt == 0) { /* DBL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) rm1 = extru(ir, fprm1pos, 5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (rm1 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) rm1 = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) rm2 = extru(ir, fprm2pos, 5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (rm2 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) rm2 = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) tm = extru(ir, fptmpos, 5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (tm == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return(MAJOR_26_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) ra = extru(ir, fprapos, 5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (ra == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return(MAJOR_26_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) ta = extru(ir, fptapos, 5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (ta == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) return(MAJOR_26_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1,&status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (dbl_fsub(&fpregs[ta], &fpregs[ra], &atmp.ints.i1,&status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return(MAJOR_26_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* copy results */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) fpregs[tm] = mtmp.ints.i1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) fpregs[tm+1] = mtmp.ints.i2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) fpregs[ta] = atmp.ints.i1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) fpregs[ta+1] = atmp.ints.i2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) fpregs[0] = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) return(NOEXCEPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) else { /* SGL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * calculate offsets for single precision numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * See table 6-14 in PA-89 architecture for mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) rm1 = (extru(ir,fprm1pos,4) | 0x10 ) << 1; /* get offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) rm1 |= extru(ir,fprm1pos-4,1); /* add right word offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) rm2 = (extru(ir,fprm2pos,4) | 0x10 ) << 1; /* get offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) rm2 |= extru(ir,fprm2pos-4,1); /* add right word offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) tm = (extru(ir,fptmpos,4) | 0x10 ) << 1; /* get offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) tm |= extru(ir,fptmpos-4,1); /* add right word offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) ra = (extru(ir,fprapos,4) | 0x10 ) << 1; /* get offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ra |= extru(ir,fprapos-4,1); /* add right word offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) ta = (extru(ir,fptapos,4) | 0x10 ) << 1; /* get offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) ta |= extru(ir,fptapos-4,1); /* add right word offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (sgl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1,&status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (sgl_fsub(&fpregs[ta], &fpregs[ra], &atmp.ints.i1,&status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return(MAJOR_26_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* copy results */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) fpregs[tm] = mtmp.ints.i1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) fpregs[ta] = atmp.ints.i1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) fpregs[0] = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return(NOEXCEPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * routine to decode the 2E (FMPYFADD,FMPYNFADD) instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static u_int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) decode_2e(ir,fpregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) u_int ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) u_int fpregs[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) u_int rm1, rm2, ra, t; /* operands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) u_int fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) fmt = extru(ir,fpfmtpos,1); /* get fmt completer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (fmt == DBL) { /* DBL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) rm1 = extru(ir,fprm1pos,5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (rm1 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) rm1 = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) rm2 = extru(ir,fprm2pos,5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (rm2 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) rm2 = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ra = ((extru(ir,fpraupos,3)<<2)|(extru(ir,fpralpos,3)>>1)) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (ra == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) ra = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) t = extru(ir,fptpos,5) * sizeof(double)/sizeof(u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (t == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return(MAJOR_2E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (extru(ir,fpfusedsubop,1)) { /* fmpyfadd or fmpynfadd? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) return(dbl_fmpynfadd(&fpregs[rm1], &fpregs[rm2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) &fpregs[ra], &fpregs[0], &fpregs[t]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) return(dbl_fmpyfadd(&fpregs[rm1], &fpregs[rm2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) &fpregs[ra], &fpregs[0], &fpregs[t]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) } /* end DBL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) else { /* SGL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) rm1 = (extru(ir,fprm1pos,5)<<1)|(extru(ir,fpxrm1pos,1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (rm1 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) rm1 = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) rm2 = (extru(ir,fprm2pos,5)<<1)|(extru(ir,fpxrm2pos,1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (rm2 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) rm2 = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) ra = (extru(ir,fpraupos,3)<<3)|extru(ir,fpralpos,3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (ra == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) ra = fpzeroreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) t = ((extru(ir,fptpos,5)<<1)|(extru(ir,fpxtpos,1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (t == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return(MAJOR_2E_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (extru(ir,fpfusedsubop,1)) { /* fmpyfadd or fmpynfadd? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) return(sgl_fmpynfadd(&fpregs[rm1], &fpregs[rm2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) &fpregs[ra], &fpregs[0], &fpregs[t]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return(sgl_fmpyfadd(&fpregs[rm1], &fpregs[rm2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) &fpregs[ra], &fpregs[0], &fpregs[t]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) } /* end SGL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * update_status_cbit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * This routine returns the correct FP status register value in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) * *status, based on the C-bit & V-bit returned by the FCMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) * emulation routine in new_status. The architecture type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) * (PA83, PA89 or PA2.0) is available in fpu_type. The y_field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) * and the architecture type are used to determine what flavor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * of FCMP is being emulated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) update_status_cbit(status, new_status, fpu_type, y_field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) u_int *status, new_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) u_int fpu_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) u_int y_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) * For PA89 FPU's which implement the Compare Queue and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * for PA2.0 FPU's, update the Compare Queue if the y-field = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * otherwise update the specified bit in the Compare Array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * Note that the y-field will always be 0 for non-PA2.0 FPU's.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if ((fpu_type & TIMEX_EXTEN_FLAG) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) (fpu_type & ROLEX_EXTEN_FLAG) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) (fpu_type & PA2_0_FPU_FLAG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (y_field == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) *status = ((*status & 0x04000000) >> 5) | /* old Cbit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ((*status & 0x003ff000) >> 1) | /* old CQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) (new_status & 0xffc007ff); /* all other bits*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) *status = (*status & 0x04000000) | /* old Cbit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) ((new_status & 0x04000000) >> (y_field+4)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) (new_status & ~0x04000000 & /* other bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) ~(0x04000000 >> (y_field+4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) /* if PA83, just update the C-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) *status = new_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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