Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *	Precise Delay Loops for parisc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	based on code by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *	Copyright (C) 1993 Linus Torvalds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *	Copyright (C) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *	Copyright (C) 2008 Jiri Hladky <hladky _dot_ jiri _at_ gmail _dot_ com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *	parisc implementation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *	Copyright (C) 2013 Helge Deller <deller@gmx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/preempt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/special_insns.h>    /* for mfctl() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/processor.h> /* for boot_cpu_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* CR16 based delay: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static void __cr16_delay(unsigned long __loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	 * Note: Due to unsigned math, cr16 rollovers shouldn't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	 * a problem here. However, on 32 bit, we need to make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	 * we don't pass in too big a value. The current default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	 * value of MAX_UDELAY_MS should help prevent this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	u32 bclock, now, loops = __loops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	bclock = mfctl(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		now = mfctl(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		if ((now - bclock) >= loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		/* Allow RT tasks to run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		asm volatile("	nop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		 * It is possible that we moved to another CPU, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		 * since CR16's are per-cpu we need to calculate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		 * that. The delay must guarantee that we wait "at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		 * least" the amount of time. Being moved to another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		 * CPU could make the wait longer but we just need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		 * make sure we waited long enough. Rebalance the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		 * counter for this CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		if (unlikely(cpu != smp_processor_id())) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 			loops -= (now - bclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 			bclock = mfctl(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void __udelay(unsigned long usecs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	__cr16_delay(usecs * ((unsigned long)boot_cpu_data.cpu_hz / 1000000UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) EXPORT_SYMBOL(__udelay);