^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _PARISC_SUPERIO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _PARISC_SUPERIO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define IC_PIC1 0x20 /* PCI I/O address of master 8259 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define IC_PIC2 0xA0 /* PCI I/O address of slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* Config Space Offsets to configuration and base address registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define SIO_CR 0x5A /* Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define SIO_ACPIBAR 0x88 /* ACPI BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SIO_FDCBAR 0x90 /* Floppy Disk Controller BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SIO_SP1BAR 0x94 /* Serial 1 BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SIO_SP2BAR 0x98 /* Serial 2 BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SIO_PPBAR 0x9C /* Parallel BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TRIGGER_1 0x67 /* Edge/level trigger register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TRIGGER_2 0x68 /* Edge/level trigger register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Interrupt Routing Control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CFG_IR_SER 0x69 /* Serial 1 [0:3] and Serial 2 [4:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CFG_IR_PFD 0x6a /* Parallel [0:3] and Floppy [4:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CFG_IR_IDE 0x6b /* IDE1 [0:3] and IDE2 [4:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CFG_IR_INTAB 0x6c /* PCI INTA [0:3] and INT B [4:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CFG_IR_INTCD 0x6d /* PCI INTC [0:3] and INT D [4:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CFG_IR_PS2 0x6e /* PS/2 KBINT [0:3] and Mouse [4:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CFG_IR_FXBUS 0x6f /* FXIRQ[0] [0:3] and FXIRQ[1] [4:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CFG_IR_USB 0x70 /* FXIRQ[2] [0:3] and USB [4:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CFG_IR_ACPI 0x71 /* ACPI SCI [0:3] and reserved [4:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CFG_IR_LOW CFG_IR_SER /* Lowest interrupt routing reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CFG_IR_HIGH CFG_IR_ACPI /* Highest interrupt routing reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* 8259 operational control words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OCW2_EOI 0x20 /* Non-specific EOI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OCW2_SEOI 0x60 /* Specific EOI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OCW3_IIR 0x0A /* Read request register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OCW3_ISR 0x0B /* Read service register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OCW3_POLL 0x0C /* Poll the PIC for an interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Interrupt lines. Only PIC1 is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define USB_IRQ 1 /* USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SP1_IRQ 3 /* Serial port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SP2_IRQ 4 /* Serial port 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PAR_IRQ 5 /* Parallel port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FDC_IRQ 6 /* Floppy controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IDE_IRQ 7 /* IDE (pri+sec) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* ACPI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define USB_REG_CR 0x1f /* USB Regulator Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SUPERIO_NIRQS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct superio_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 fdc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 sp1_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 sp2_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 pp_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 acpi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int suckyio_irq_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct pci_dev *lio_pdev; /* pci device for legacy IO (fn 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct pci_dev *usb_pdev; /* pci device for USB (fn 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Does NS make a 87415 based plug in PCI card? If so, because of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * macro we currently don't support it being plugged into a machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * that contains a SuperIO chip AND has CONFIG_SUPERIO enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * This could be fixed by checking to see if function 1 exists, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * if it is SuperIO Legacy IO; but really now, is this combination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * going to EVER happen?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SUPERIO_IDE_FN 0 /* Function number of IDE controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SUPERIO_LIO_FN 1 /* Function number of Legacy IO controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SUPERIO_USB_FN 2 /* Function number of USB controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define is_superio_device(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) (((x)->vendor == PCI_VENDOR_ID_NS) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ( ((x)->device == PCI_DEVICE_ID_NS_87415) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) || ((x)->device == PCI_DEVICE_ID_NS_87560_LIO) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) || ((x)->device == PCI_DEVICE_ID_NS_87560_USB) ) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) extern int superio_fixup_irq(struct pci_dev *pcidev); /* called by iosapic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #endif /* _PARISC_SUPERIO_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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