^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_PARISC_ROPES_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_PARISC_ROPES_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/parisc-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define ZX1_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* depends on proc fs support. But costs CPU performance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #undef SBA_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ** The number of pdir entries to "free" before issuing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ** a read to PCOM register to flush out PCOM writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ** Interacts with allocation granularity (ie 4 or 8 entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ** allocated and free'd/purged at a time might make this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ** less interesting).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DELAYED_RESOURCE_CNT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct ioc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *ioc_hpa; /* I/O MMU base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) char *res_map; /* resource map, bit == pdir entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u64 *pdir_base; /* physical base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #ifdef ZX1_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned long iovp_mask; /* help convert IOVA to IOVP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long *res_hint; /* next avail IOVP - circular search */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) spinlock_t res_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int res_bitshift; /* from the LEFT! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int res_size; /* size of resource map in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #ifdef SBA_HINT_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* FIXME : DMA HINTs not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long hint_mask_pdir; /* bits used for DMA hints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int hint_shift_pdir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #if DELAYED_RESOURCE_CNT > 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int saved_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct sba_dma_pair {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) dma_addr_t iova;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } saved[DELAYED_RESOURCE_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #ifdef SBA_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SBA_SEARCH_SAMPLE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long avg_search[SBA_SEARCH_SAMPLE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned long avg_idx; /* current index into avg_search */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long used_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned long msingle_calls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long msingle_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long msg_calls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long msg_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long usingle_calls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned long usingle_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long usg_calls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long usg_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* STUFF We don't need in performance path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int pdir_size; /* in bytes, determined by IOV Space size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct sba_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct sba_device *next; /* list of SBA's in system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct parisc_device *dev; /* dev found in bus walk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void __iomem *sba_hpa; /* base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) spinlock_t sba_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int flags; /* state/functionality enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int hw_rev; /* HW revision of chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct resource chip_resv; /* MMIO reserved for chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct resource iommu_resv; /* MMIO reserved for iommu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int num_ioc; /* number of on-board IOC's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct ioc ioc[MAX_IOC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ASTRO_RUNWAY_PORT 0x582
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IKE_MERCED_PORT 0x803
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define REO_MERCED_PORT 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define REOG_MERCED_PORT 0x805
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PLUTO_MCKINLEY_PORT 0x880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static inline int IS_ASTRO(struct parisc_device *d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return d->id.hversion == ASTRO_RUNWAY_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static inline int IS_IKE(struct parisc_device *d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return d->id.hversion == IKE_MERCED_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline int IS_PLUTO(struct parisc_device *d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return d->id.hversion == PLUTO_MCKINLEY_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PLUTO_IOVA_BASE (1UL*1024*1024*1024) /* 1GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PLUTO_IOVA_SIZE (1UL*1024*1024*1024) /* 1GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PLUTO_GART_SIZE (PLUTO_IOVA_SIZE / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SBA_PDIR_VALID_BIT 0x8000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SBA_AGPGART_COOKIE 0x0000badbadc0ffeeULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SBA_FUNC_ID 0x0000 /* function id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Ike's IOC's occupy functions 2 and 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IOC_CTRL 0x8 /* IOC_CTRL offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IOC_CTRL_TC (1 << 0) /* TOC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IOC_CTRL_RM (1 << 8) /* Real Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ** Firmware programs this stuff. Don't touch it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define LMMIO_DIRECT0_BASE 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define LMMIO_DIRECT0_MASK 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define LMMIO_DIRECT0_ROUTE 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LMMIO_DIST_BASE 0x360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LMMIO_DIST_MASK 0x368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LMMIO_DIST_ROUTE 0x370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IOS_DIST_BASE 0x390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IOS_DIST_MASK 0x398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IOS_DIST_ROUTE 0x3A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IOS_DIRECT_BASE 0x3C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IOS_DIRECT_MASK 0x3C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IOS_DIRECT_ROUTE 0x3D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ** Offsets into I/O TLB (Function 2 and 3 on Ike)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ROPE0_CTL 0x200 /* "regbus pci0" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ROPE1_CTL 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ROPE2_CTL 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ROPE3_CTL 0x218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ROPE4_CTL 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ROPE5_CTL 0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ROPE6_CTL 0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ROPE7_CTL 0x238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IOC_ROPE0_CFG 0x500 /* pluto only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define HF_ENABLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IOC_IBASE 0x300 /* IO TLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IOC_IMASK 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IOC_PCOM 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IOC_TCNFG 0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IOC_PDIR_BASE 0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ** It's safer (avoid memory corruption) to keep DMA page mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ** equivalently sized to VM PAGE_SIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ** We really can't avoid generating a new mapping for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ** page since the Virtual Coherence Index has to be generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ** and updated for each page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IOVP_SIZE PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IOVP_SHIFT PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IOVP_MASK PAGE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SBA_PERF_CFG 0x708 /* Performance Counter stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SBA_PERF_MASK1 0x718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SBA_PERF_MASK2 0x730
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ** Offsets into PCI Performance Counters (functions 12 and 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ** Controlled by PERF registers in function 2 & 3 respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SBA_PERF_CNT1 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SBA_PERF_CNT2 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SBA_PERF_CNT3 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ** lba_device: Per instance Elroy data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct lba_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct pci_hba_data hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) spinlock_t lba_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) void *iosapic_obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) void __iomem *iop_base; /* PA_VIEW - for IO port accessor funcs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int flags; /* state/functionality enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int hw_rev; /* HW revision of chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ELROY_HVERS 0x782
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MERCURY_HVERS 0x783
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define QUICKSILVER_HVERS 0x784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static inline int IS_ELROY(struct parisc_device *d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return (d->id.hversion == ELROY_HVERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static inline int IS_MERCURY(struct parisc_device *d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return (d->id.hversion == MERCURY_HVERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static inline int IS_QUICKSILVER(struct parisc_device *d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return (d->id.hversion == QUICKSILVER_HVERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static inline int agp_mode_mercury(void __iomem *hpa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u64 bus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) bus_mode = readl(hpa + 0x0620);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (bus_mode & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ** I/O SAPIC init function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ** Call setup as part of per instance initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ** (ie *not* init_module() function unless only one is present.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ** fixup_irq is to initialize PCI IRQ line support and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ** virtualize pcidev->irq value. To be called by pci_fixup_bus().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) extern void *iosapic_register(unsigned long hpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) extern int iosapic_fixup_irq(void *obj, struct pci_dev *pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define LBA_FUNC_ID 0x0000 /* function id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define LBA_CAPABLE 0x0030 /* capabilities register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define LBA_ARB_PRI 0x0088 /* firmware sets this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define LBA_ARB_MODE 0x0090 /* firmware sets this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define LBA_ARB_MTLT 0x0098 /* firmware sets this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define LBA_STAT_CTL 0x0108 /* Status & Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define LBA_LMMIO_MASK 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define LBA_GMMIO_MASK 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define LBA_WLMMIO_MASK 0x0228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define LBA_WGMMIO_MASK 0x0238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define LBA_IOS_MASK 0x0248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define LBA_ELMMIO_MASK 0x0258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define LBA_EIOS_MASK 0x0268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define LBA_GLOBAL_MASK 0x0270 /* Mercury only: Global Address Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define LBA_DMA_CTL 0x0278 /* firmware sets this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define LBA_IBASE 0x0300 /* SBA DMA support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define LBA_IMASK 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* FIXME: ignore DMA Hint stuff until we can measure performance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define LBA_HINT_CFG 0x0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define LBA_BUS_MODE 0x0620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* ERROR regs are needed for config cycle kluges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define LBA_ERROR_CONFIG 0x0680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define LBA_SMART_MODE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define LBA_ERROR_STATUS 0x0688
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define LBA_ROPE_CTL 0x06A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #endif /*_ASM_PARISC_ROPES_H_*/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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