Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * include/asm-parisc/prefetch.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * PA 2.0 defines data prefetch instructions on page 6-11 of the Kane book.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * In addition, many implementations do hardware prefetching of both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * instructions and data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * PA7300LC (page 14-4 of the ERS) also implements prefetching by a load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * to gr0 but not in a way that Linux can use.  If the load would cause an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * interruption (eg due to prefetching 0), it is suppressed on PA2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * processors, but not on 7300LC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef __ASM_PARISC_PREFETCH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define __ASM_PARISC_PREFETCH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifdef CONFIG_PREFETCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ARCH_HAS_PREFETCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static inline void prefetch(const void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	__asm__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifndef CONFIG_PA20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		/* Need to avoid prefetch of NULL on PA7300LC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		"	extrw,u,= %0,31,32,%%r0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		"	ldw 0(%0), %%r0" : : "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* LDD is a PA2.0 addition. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifdef CONFIG_PA20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ARCH_HAS_PREFETCHW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static inline void prefetchw(const void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	__asm__("ldd 0(%0), %%r0" : : "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif /* CONFIG_PA20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif /* CONFIG_PREFETCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif /* __ASM_PARISC_PROCESSOR_H */