^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _PARISC_PGTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _PARISC_PGTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #if CONFIG_PGTABLE_LEVELS == 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm-generic/pgtable-nopud.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #elif CONFIG_PGTABLE_LEVELS == 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm-generic/pgtable-nopmd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/fixmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * we simulate an x86-style page table for the linux mm code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mm_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static inline spinlock_t *pgd_spinlock(pgd_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * memory. For the return value to be meaningful, ADDR must be >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * require a hash-, or multi-level tree-lookup or something of that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * sort) but it guarantees to return TRUE only if accessing the page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * at that address does not cause an error. Note that there may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * addresses for which kern_addr_valid() returns FALSE even though an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * access would not cause an error (e.g., this is typically true for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * memory mapped I/O regions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * XXX Need to implement this for parisc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define kern_addr_valid(addr) (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* This is for the serialization of PxTLB broadcasts. At least on the N class
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * systems, only one PxTLB inter processor broadcast can be active at any one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * time on the Merced bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * PTE updates are protected by locks in the PMD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) extern spinlock_t pa_tlb_flush_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) extern spinlock_t pa_swapper_pg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #if defined(CONFIG_64BIT) && defined(CONFIG_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) extern int pa_serialize_tlb_flushes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define pa_serialize_tlb_flushes (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define purge_tlb_start(flags) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (pa_serialize_tlb_flushes) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) spin_lock_irqsave(&pa_tlb_flush_lock, flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) local_irq_save(flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define purge_tlb_end(flags) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (pa_serialize_tlb_flushes) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) spin_unlock_irqrestore(&pa_tlb_flush_lock, flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) local_irq_restore(flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Purge data and instruction TLB entries. The TLB purge instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * are slow on SMP machines since the purge must be broadcast to all CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static inline void purge_tlb_entries(struct mm_struct *mm, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) purge_tlb_start(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) mtsp(mm->context, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pdtlb(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pitlb(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) purge_tlb_end(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Certain architectures need to do special things when PTEs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * within a page table are directly modified. Thus, the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * hook is made available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define set_pte(pteptr, pteval) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) do{ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *(pteptr) = (pteval); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define set_pte_at(mm, addr, ptep, pteval) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) spin_lock_irqsave(pgd_spinlock((mm)->pgd), flags);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) set_pte(ptep, pteval); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) purge_tlb_entries(mm, addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) spin_unlock_irqrestore(pgd_spinlock((mm)->pgd), flags);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif /* !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define pte_ERROR(e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #if CONFIG_PGTABLE_LEVELS == 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define pmd_ERROR(e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define pgd_ERROR(e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* This is the size of the initially mapped kernel memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #if defined(CONFIG_64BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define KERNEL_INITIAL_ORDER 26 /* 1<<26 = 64MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define KERNEL_INITIAL_ORDER 25 /* 1<<25 = 32MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #if CONFIG_PGTABLE_LEVELS == 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PGD_ORDER 1 /* Number of pages per pgd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PMD_ORDER 1 /* Number of pages per pmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PGD_ALLOC_ORDER (2 + 1) /* first pgd contains pmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PGD_ORDER 1 /* Number of pages per pgd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PGD_ALLOC_ORDER (PGD_ORDER + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Definitions for 3rd level (we use PLD here for Page Lower directory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * because PTE_SHIFT is used lower down to mean shift that has to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * done to get usable bits out of the PTE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PLD_SHIFT PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PLD_SIZE PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PTRS_PER_PTE (1UL << BITS_PER_PTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Definitions for 2nd level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #if CONFIG_PGTABLE_LEVELS == 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PMD_SIZE (1UL << PMD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PMD_MASK (~(PMD_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PTRS_PER_PMD (1UL << BITS_PER_PMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define BITS_PER_PMD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Definitions for 1st level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PGDIR_SHIFT (PLD_SHIFT + BITS_PER_PTE + BITS_PER_PMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #if (PGDIR_SHIFT + PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) > BITS_PER_LONG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define BITS_PER_PGD (BITS_PER_LONG - PGDIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define BITS_PER_PGD (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PGDIR_MASK (~(PGDIR_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PTRS_PER_PGD (1UL << BITS_PER_PGD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define USER_PTRS_PER_PGD PTRS_PER_PGD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MAX_ADDRESS (1UL << MAX_ADDRBITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SPACEID_SHIFT (MAX_ADDRBITS - 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MAX_ADDRBITS (BITS_PER_LONG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MAX_ADDRESS (1UL << MAX_ADDRBITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SPACEID_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* This calculates the number of initial pages we need for the initial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * page tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #if (KERNEL_INITIAL_ORDER) >= (PMD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) # define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) # define PT_INITIAL (1) /* all initial PTEs fit into one page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * pgd entries used up by user/kernel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define FIRST_USER_ADDRESS 0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* NB: The tlb miss handlers make certain assumptions about the order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* of the following bits, so be careful (One example, bits 25-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* are moved together in one instruction). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define _PAGE_READ_BIT 31 /* (0x001) read access allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define _PAGE_HPAGE_BIT 21 /* (0x400) Software: Huge Page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* N.B. The bits are defined in terms of a 32 bit word above, so the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* following macro is ok for both 32 and 64 bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define xlate_pabit(x) (31 - x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* this defines the shift to the usable bits in the PTE it is set so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PFN_PTE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define _PAGE_HUGE (1 << xlate_pabit(_PAGE_HPAGE_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define _PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_DIRTY | _PAGE_ACCESSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define _PAGE_KERNEL_EXEC (_PAGE_KERNEL_RO | _PAGE_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define _PAGE_KERNEL_RWX (_PAGE_KERNEL_EXEC | _PAGE_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define _PAGE_KERNEL (_PAGE_KERNEL_RO | _PAGE_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * are page-aligned, we don't care about the PAGE_OFFSET bits, except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * for a few meta-information bits, so we shift the address to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * able to effectively address 40/42/44-bits of physical address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * depending on 4k/16k/64k PAGE_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define _PxD_PRESENT_BIT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define _PxD_ATTACHED_BIT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define _PxD_VALID_BIT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PxD_FLAG_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define PxD_FLAG_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PxD_VALUE_SHIFT (PFN_PTE_SHIFT-PxD_FLAG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Others seem to make this executable, I don't know if that's correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) or not. The stack is mapped this way though so this is necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) in the short term - dhd@linuxcare.com, 2000-08-08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define PAGE_COPY PAGE_EXECREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define PAGE_KERNEL_RWX __pgprot(_PAGE_KERNEL_RWX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_GATEWAY| _PAGE_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * We could have an execute only page using "gateway - promote to priv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * level 3", but that is kind of silly. So, the way things are defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * now, we must always have read permission for pages with execute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * permission. For the fun of it we'll go ahead and support write only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*xwr*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define __P000 PAGE_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define __P001 PAGE_READONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define __P010 __P000 /* copy on write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define __P011 __P001 /* copy on write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define __P100 PAGE_EXECREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define __P101 PAGE_EXECREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define __P110 __P100 /* copy on write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define __P111 __P101 /* copy on write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define __S000 PAGE_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define __S001 PAGE_READONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define __S010 PAGE_WRITEONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define __S011 PAGE_SHARED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define __S100 PAGE_EXECREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define __S101 PAGE_EXECREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define __S110 PAGE_RWX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define __S111 PAGE_RWX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* initial page tables for 0-8MB for kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) extern pte_t pg0[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* zero page used for uninitialized stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) extern unsigned long *empty_zero_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * ZERO_PAGE is a global shared page that is always zero: used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * for zero-mapped memory areas etc..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define pte_none(x) (pte_val(x) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define pte_clear(mm, addr, xp) set_pte_at(mm, addr, xp, __pte(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define pud_flag(x) (pud_val(x) & PxD_FLAG_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define pud_address(x) ((unsigned long)(pud_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #if CONFIG_PGTABLE_LEVELS == 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* The first entry of the permanent pmd is not there if it contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * the gateway marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define pmd_none(x) (!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define pmd_none(x) (!pmd_val(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static inline void pmd_clear(pmd_t *pmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #if CONFIG_PGTABLE_LEVELS == 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* This is the entry pointing to the permanent pmd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * attached to the pgd; cannot clear it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) set_pmd(pmd, __pmd(PxD_FLAG_ATTACHED));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) set_pmd(pmd, __pmd(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #if CONFIG_PGTABLE_LEVELS == 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define pud_page_vaddr(pud) ((unsigned long) __va(pud_address(pud)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* For 64 bit we have three level tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define pud_none(x) (!pud_val(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define pud_bad(x) (!(pud_flag(x) & PxD_FLAG_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define pud_present(x) (pud_flag(x) & PxD_FLAG_PRESENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static inline void pud_clear(pud_t *pud) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #if CONFIG_PGTABLE_LEVELS == 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if(pud_flag(*pud) & PxD_FLAG_ATTACHED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* This is the permanent pmd attached to the pud; cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * free it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) set_pud(pud, __pud(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * The following only work if pte_present() is true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * Undefined behaviour if not..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * Huge pte definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #ifdef CONFIG_HUGETLB_PAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define pte_huge(pte) (pte_val(pte) & _PAGE_HUGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define pte_mkhuge(pte) (__pte(pte_val(pte) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) (parisc_requires_coherency() ? 0 : _PAGE_HUGE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define pte_huge(pte) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define pte_mkhuge(pte) (pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * Conversion functions: convert a page and protection to a page entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * and a page entry and page directory to the page they refer to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define __mk_pte(addr,pgprot) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pte_t __pte; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) __pte; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pte_t pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Permanent address of a page. On parisc we don't have highmem. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static inline unsigned long pmd_page_vaddr(pmd_t pmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return ((unsigned long) __va(pmd_address(pmd)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Find an entry in the second-level page table.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) extern void paging_init (void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* Used for deferring calls to flush_dcache_page() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define PG_dcache_dirty PG_arch_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Encode and de-code a swap entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define __swp_type(x) ((x).val & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define __swp_offset(x) ( (((x).val >> 6) & 0x7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) (((x).val >> 8) & ~0x7) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define __swp_entry(type, offset) ((swp_entry_t) { (type) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ((offset & 0x7) << 6) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ((offset & ~0x7) << 8) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static inline spinlock_t *pgd_spinlock(pgd_t *pgd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (unlikely(pgd == swapper_pg_dir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return &pa_swapper_pg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return (spinlock_t *)((char *)pgd + (PAGE_SIZE << (PGD_ALLOC_ORDER - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pte_t pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (!pte_young(*ptep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) spin_lock_irqsave(pgd_spinlock(vma->vm_mm->pgd), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) pte = *ptep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (!pte_young(pte)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) spin_unlock_irqrestore(pgd_spinlock(vma->vm_mm->pgd), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) set_pte(ptep, pte_mkold(pte));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) purge_tlb_entries(vma->vm_mm, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) spin_unlock_irqrestore(pgd_spinlock(vma->vm_mm->pgd), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct mm_struct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) pte_t old_pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) spin_lock_irqsave(pgd_spinlock(mm->pgd), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) old_pte = *ptep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) set_pte(ptep, __pte(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) purge_tlb_entries(mm, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) spin_unlock_irqrestore(pgd_spinlock(mm->pgd), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return old_pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) spin_lock_irqsave(pgd_spinlock(mm->pgd), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) set_pte(ptep, pte_wrprotect(*ptep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) purge_tlb_entries(mm, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) spin_unlock_irqrestore(pgd_spinlock(mm->pgd), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define pte_same(A,B) (pte_val(A) == pte_val(B))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct seq_file;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) extern void arch_report_meminfo(struct seq_file *m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #endif /* !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* TLB page size encoding - see table 3-1 in parisc20.pdf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define _PAGE_SIZE_ENCODING_4K 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define _PAGE_SIZE_ENCODING_16K 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define _PAGE_SIZE_ENCODING_64K 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define _PAGE_SIZE_ENCODING_256K 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define _PAGE_SIZE_ENCODING_1M 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define _PAGE_SIZE_ENCODING_4M 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define _PAGE_SIZE_ENCODING_16M 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define _PAGE_SIZE_ENCODING_64M 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #elif defined(CONFIG_PARISC_PAGE_SIZE_16KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #elif defined(CONFIG_PARISC_PAGE_SIZE_64KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* We provide our own get_unmapped_area to provide cache coherency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define HAVE_ARCH_UNMAPPED_AREA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define __HAVE_ARCH_PTEP_SET_WRPROTECT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define __HAVE_ARCH_PTE_SAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #endif /* _PARISC_PGTABLE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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