Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _ASM_PERF_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _ASM_PERF_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /* ioctls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define PA_PERF_ON	_IO('p', 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define PA_PERF_OFF	_IOR('p', 2, unsigned int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define PA_PERF_VERSION	_IOR('p', 3, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PA_PERF_DEV	"perf"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PA_PERF_MINOR	146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Interface types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define UNKNOWN_INTF    255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ONYX_INTF         0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CUDA_INTF         1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Common Onyx and Cuda images */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CPI                 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BUSUTIL             1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TLBMISS             2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TLBHANDMISS         3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PTKN                4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PNTKN               5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMISS               6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DMISS               7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DMISS_ACCESS        8 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BIG_CPI 	    9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BIG_LS		   10  
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BR_ABORT	   11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ISNT		   12 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define QUADRANT           13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RW_PDFET           14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RW_WDFET           15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SHLIB_CPI          16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Cuda only Images */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FLOPS              17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CACHEMISS          18 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BRANCHES           19             
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CRSTACK            20 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I_CACHE_SPEC       21 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MAX_CUDA_IMAGES    22 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Onyx only Images */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ADDR_INV_ABORT_ALU 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BRAD_STALL	   18 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CNTL_IN_PIPEL	   19 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DSNT_XFH	   20 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FET_SIG1	   21 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FET_SIG2	   22 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define G7_1		   23 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define G7_2		   24 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define G7_3 		   25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define G7_4		   26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MPB_LABORT         27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PANIC              28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RARE_INST          29 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RW_DFET            30 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RW_IFET            31 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RW_SDFET           32 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPEC_IFET          33 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ST_COND0           34 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ST_COND1           35 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ST_COND2           36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ST_COND3           37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ST_COND4           38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ST_UNPRED0         39 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ST_UNPRED1         40 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define UNPRED             41 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GO_STORE           42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SHLIB_CALL         43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MAX_ONYX_IMAGES    44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #endif