^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) #ifndef __PARISC_PATPDC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #define __PARISC_PATPDC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2000 (c) Hewlett Packard (Paul Bame <bame()spam.parisc-linux.org>)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright 2000,2004 (c) Grant Grundler <grundler()nahspam.parisc-linux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PDC_PAT_CELL 64L /* Interface for gaining and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * manipulatin g cell state within PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PDC_PAT_CELL_GET_NUMBER 0L /* Return Cell number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PDC_PAT_CELL_GET_INFO 1L /* Returns info about Cell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PDC_PAT_CELL_MODULE 2L /* Returns info about Module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PDC_PAT_CELL_SET_ATTENTION 9L /* Set Cell Attention indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PDC_PAT_CELL_NUMBER_TO_LOC 10L /* Cell Number -> Location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PDC_PAT_CELL_WALK_FABRIC 11L /* Walk the Fabric */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PDC_PAT_CELL_GET_RDT_SIZE 12L /* Return Route Distance Table Sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PDC_PAT_CELL_GET_RDT 13L /* Return Route Distance Tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PDC_PAT_CELL_GET_LOCAL_PDH_SZ 14L /* Read Local PDH Buffer Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PDC_PAT_CELL_SET_LOCAL_PDH 15L /* Write Local PDH Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PDC_PAT_CELL_GET_REMOTE_PDH_SZ 16L /* Return Remote PDH Buffer Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PDC_PAT_CELL_GET_REMOTE_PDH 17L /* Read Remote PDH Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PDC_PAT_CELL_GET_DBG_INFO 128L /* Return DBG Buffer Info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PDC_PAT_CELL_CHANGE_ALIAS 129L /* Change Non-Equivalent Alias Chacking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ** Arg to PDC_PAT_CELL_MODULE memaddr[4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ** Addresses on the Merced Bus != all Runway Bus addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ** This is intended for programming SBA/LBA chips range registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IO_VIEW 0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PA_VIEW 1UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* PDC_PAT_CELL_MODULE entity type values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PAT_ENTITY_CA 0 /* central agent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PAT_ENTITY_PROC 1 /* processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PAT_ENTITY_MEM 2 /* memory controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PAT_ENTITY_SBA 3 /* system bus adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PAT_ENTITY_LBA 4 /* local bus adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PAT_ENTITY_PBC 5 /* processor bus converter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PAT_ENTITY_XBC 6 /* crossbar fabric connect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PAT_ENTITY_RC 7 /* fabric interconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* PDC_PAT_CELL_MODULE address range type values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PAT_PBNUM 0 /* PCI Bus Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PAT_LMMIO 1 /* < 4G MMIO Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PAT_GMMIO 2 /* > 4G MMIO Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PAT_NPIOP 3 /* Non Postable I/O Port Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PAT_PIOP 4 /* Postable I/O Port Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PAT_AHPA 5 /* Addional HPA Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PAT_UFO 6 /* HPA Space (UFO for Mariposa) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PAT_GNIP 7 /* GNI Reserved Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* PDC PAT CHASSIS LOG -- Platform logging & forward progress functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PDC_PAT_CHASSIS_LOG 65L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PDC_PAT_CHASSIS_WRITE_LOG 0L /* Write Log Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PDC_PAT_CHASSIS_READ_LOG 1L /* Read Log Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* PDC PAT COMPLEX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PDC_PAT_COMPLEX 66L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* PDC PAT CPU -- CPU configuration within the protection domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PDC_PAT_CPU 67L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PDC_PAT_CPU_INFO 0L /* Return CPU config info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PDC_PAT_CPU_DELETE 1L /* Delete CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PDC_PAT_CPU_ADD 2L /* Add CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PDC_PAT_CPU_GET_NUMBER 3L /* Return CPU Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PDC_PAT_CPU_GET_HPA 4L /* Return CPU HPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PDC_PAT_CPU_STOP 5L /* Stop CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PDC_PAT_CPU_RENDEZVOUS 6L /* Rendezvous CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PDC_PAT_CPU_GET_CLOCK_INFO 7L /* Return CPU Clock info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PDC_PAT_CPU_GET_RENDEZVOUS_STATE 8L /* Return Rendezvous State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PDC_PAT_CPU_PLUNGE_FABRIC 128L /* Plunge Fabric */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PDC_PAT_CPU_UPDATE_CACHE_CLEANSING 129L /* Manipulate Cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Cleansing Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* PDC PAT EVENT -- Platform Events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PDC_PAT_EVENT 68L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PDC_PAT_EVENT_GET_CAPS 0L /* Get Capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PDC_PAT_EVENT_SET_MODE 1L /* Set Notification Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PDC_PAT_EVENT_SCAN 2L /* Scan Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PDC_PAT_EVENT_HANDLE 3L /* Handle Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PDC_PAT_EVENT_GET_NB_CALL 4L /* Get Non-Blocking call Args */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* PDC PAT HPMC -- Cause processor to go into spin loop, and wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * for wake up from Monarch Processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PDC_PAT_HPMC 70L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PDC_PAT_HPMC_RENDEZ_CPU 0L /* go into spin loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PDC_PAT_HPMC_SET_PARAMS 1L /* Allows OS to specify intr which PDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * will use to interrupt OS during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * machine check rendezvous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* parameters for PDC_PAT_HPMC_SET_PARAMS: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HPMC_SET_PARAMS_INTR 1L /* Rendezvous Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HPMC_SET_PARAMS_WAKE 2L /* Wake up processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* PDC PAT IO -- On-line services for I/O modules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PDC_PAT_IO 71L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PDC_PAT_IO_GET_SLOT_STATUS 5L /* Get Slot Status Info*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PDC_PAT_IO_GET_LOC_FROM_HARDWARE 6L /* Get Physical Location from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Hardware Path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PDC_PAT_IO_GET_HARDWARE_FROM_LOC 7L /* Get Hardware Path from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Physical Location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PDC_PAT_IO_GET_PCI_CONFIG_FROM_HW 11L /* Get PCI Configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Address from Hardware Path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PDC_PAT_IO_GET_HW_FROM_PCI_CONFIG 12L /* Get Hardware Path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * from PCI Configuration Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PDC_PAT_IO_READ_HOST_BRIDGE_INFO 13L /* Read Host Bridge State Info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PDC_PAT_IO_CLEAR_HOST_BRIDGE_INFO 14L /* Clear Host Bridge State Info*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PDC_PAT_IO_GET_PCI_ROUTING_TABLE_SIZE 15L /* Get PCI INT Routing Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PDC_PAT_IO_GET_PCI_ROUTING_TABLE 16L /* Get PCI INT Routing Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PDC_PAT_IO_GET_HINT_TABLE_SIZE 17L /* Get Hint Table Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PDC_PAT_IO_GET_HINT_TABLE 18L /* Get Hint Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PDC_PAT_IO_PCI_CONFIG_READ 19L /* PCI Config Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PDC_PAT_IO_PCI_CONFIG_WRITE 20L /* PCI Config Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PDC_PAT_IO_GET_NUM_IO_SLOTS 21L /* Get Number of I/O Bay Slots in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Cabinet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PDC_PAT_IO_GET_LOC_IO_SLOTS 22L /* Get Physical Location of I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Bay Slots in Cabinet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PDC_PAT_IO_BAY_STATUS_INFO 28L /* Get I/O Bay Slot Status Info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PDC_PAT_IO_GET_PROC_VIEW 29L /* Get Processor view of IO address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PDC_PAT_IO_PROG_SBA_DIR_RANGE 30L /* Program directed range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* PDC PAT MEM -- Manage memory page deallocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PDC_PAT_MEM 72L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PDC_PAT_MEM_PD_INFO 0L /* Return PDT info for PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PDC_PAT_MEM_PD_CLEAR 1L /* Clear PDT for PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PDC_PAT_MEM_PD_READ 2L /* Read PDT entries for PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PDC_PAT_MEM_PD_RESET 3L /* Reset clear bit for PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PDC_PAT_MEM_CELL_INFO 5L /* Return PDT info For Cell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PDC_PAT_MEM_CELL_CLEAR 6L /* Clear PDT For Cell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PDC_PAT_MEM_CELL_READ 7L /* Read PDT entries For Cell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PDC_PAT_MEM_CELL_RESET 8L /* Reset clear bit For Cell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PDC_PAT_MEM_SETGM 9L /* Set Good Memory value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PDC_PAT_MEM_ADD_PAGE 10L /* ADDs a page to the cell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PDC_PAT_MEM_ADDRESS 11L /* Get Physical Location From */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Memory Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PDC_PAT_MEM_GET_TXT_SIZE 12L /* Get Formatted Text Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PDC_PAT_MEM_GET_PD_TXT 13L /* Get PD Formatted Text */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PDC_PAT_MEM_GET_CELL_TXT 14L /* Get Cell Formatted Text */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PDC_PAT_MEM_RD_STATE_INFO 15L /* Read Mem Module State Info*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PDC_PAT_MEM_CLR_STATE_INFO 16L /*Clear Mem Module State Info*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PDC_PAT_MEM_CLEAN_RANGE 128L /*Clean Mem in specific range*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PDC_PAT_MEM_GET_TBL_SIZE 131L /* Get Memory Table Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PDC_PAT_MEM_GET_TBL 132L /* Get Memory Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* PDC PAT NVOLATILE -- Access Non-Volatile Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PDC_PAT_NVOLATILE 73L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PDC_PAT_NVOLATILE_READ 0L /* Read Non-Volatile Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PDC_PAT_NVOLATILE_WRITE 1L /* Write Non-Volatile Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PDC_PAT_NVOLATILE_GET_SIZE 2L /* Return size of NVM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PDC_PAT_NVOLATILE_VERIFY 3L /* Verify contents of NVM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PDC_PAT_NVOLATILE_INIT 4L /* Initialize NVM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* PDC PAT PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PDC_PAT_PD 74L /* Protection Domain Info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PDC_PAT_PD_GET_ADDR_MAP 0L /* Get Address Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PDC_PAT_PD_GET_PDC_INTERF_REV 1L /* Get PDC Interface Revisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PDC_PAT_CAPABILITY_BIT_PDC_SERIALIZE (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PDC_PAT_CAPABILITY_BIT_PDC_POLLING (1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PDC_PAT_CAPABILITY_BIT_PDC_NBC (1UL << 2) /* non-blocking calls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PDC_PAT_CAPABILITY_BIT_PDC_UFO (1UL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PDC_PAT_CAPABILITY_BIT_PDC_IODC_32 (1UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PDC_PAT_CAPABILITY_BIT_PDC_IODC_64 (1UL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PDC_PAT_CAPABILITY_BIT_PDC_HPMC_RENDEZ (1UL << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PDC_PAT_CAPABILITY_BIT_SIMULTANEOUS_PTLB (1UL << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* PDC_PAT_PD_GET_ADDR_MAP entry types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PAT_MEMORY_DESCRIPTOR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* PDC_PAT_PD_GET_ADDR_MAP memory types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PAT_MEMTYPE_MEMORY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PAT_MEMTYPE_FIRMWARE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* PDC_PAT_PD_GET_ADDR_MAP memory usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PAT_MEMUSE_GENERAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PAT_MEMUSE_GI 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define PAT_MEMUSE_GNI 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* PDC PAT REGISTER TOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PDC_PAT_REGISTER_TOC 75L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define PDC_PAT_TOC_REGISTER_VECTOR 0L /* Register TOC Vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define PDC_PAT_TOC_READ_VECTOR 1L /* Read TOC Vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* PDC PAT SYSTEM_INFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PDC_PAT_SYSTEM_INFO 76L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* PDC_PAT_SYSTEM_INFO uses the same options as PDC_SYSTEM_INFO function. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define is_pdc_pat() (PDC_TYPE_PAT == pdc_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) extern int pdc_pat_get_irt_size(unsigned long *num_entries, unsigned long cell_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) extern int pdc_pat_get_irt(void *r_addr, unsigned long cell_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #else /* ! CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* No PAT support for 32-bit kernels...sorry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define is_pdc_pat() (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define pdc_pat_get_irt_size(num_entries, cell_numn) PDC_BAD_PROC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define pdc_pat_get_irt(r_addr, cell_num) PDC_BAD_PROC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #endif /* ! CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct pdc_pat_cell_num {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned long cell_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned long cell_loc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct pdc_pat_cpu_num {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned long cpu_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned long cpu_loc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct pdc_pat_mem_retinfo { /* PDC_PAT_MEM/PDC_PAT_MEM_PD_INFO (return info) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int ke; /* bit 0: memory inside good memory? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned int current_pdt_entries:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned int max_pdt_entries:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned long Cs_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned long Ic_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned long good_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned long first_dbe_loc; /* first location of double bit error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned long clear_time; /* last PDT clear time (since Jan 1970) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct pdc_pat_mem_cell_pdt_retinfo { /* PDC_PAT_MEM/PDC_PAT_MEM_CELL_INFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u64 reserved:32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u64 cs:1; /* clear status: cleared since the last call? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u64 current_pdt_entries:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u64 ic:1; /* interleaving had to be changed ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u64 max_pdt_entries:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned long good_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned long first_dbe_loc; /* first location of double bit error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned long clear_time; /* last PDT clear time (since Jan 1970) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct pdc_pat_mem_read_pd_retinfo { /* PDC_PAT_MEM/PDC_PAT_MEM_PD_READ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned long actual_count_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long pdt_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct pdc_pat_mem_phys_mem_location { /* PDC_PAT_MEM/PDC_PAT_MEM_ADDRESS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u64 cabinet:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u64 ign1:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u64 ign2:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u64 cell_slot:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u64 ign3:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u64 dimm_slot:8; /* DIMM slot, e.g. 0x1A, 0x2B, show user hex value! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u64 ign4:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u64 source:4; /* for mem: always 0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u64 source_detail:4; /* for mem: always 0x04 (SIMM or DIMM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct pdc_pat_pd_addr_map_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned char entry_type; /* 1 = Memory Descriptor Entry Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned char reserve1[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned char memory_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned char memory_usage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned long paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned int pages; /* Length in 4K pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned int reserve2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned long cell_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * PDC_PAT_CELL[Return Cell Module] memaddr[0] conf_base_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * ----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * Bit 0 to 51 - conf_base_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * Bit 52 to 62 - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * Bit 63 - endianess bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define PAT_GET_CBA(value) ((value) & 0xfffffffffffff000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * PDC_PAT_CELL[Return Cell Module] memaddr[1] mod_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * ----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Bit 0 to 7 - entity type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * 0 = central agent, 1 = processor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * 2 = memory controller, 3 = system bus adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * 4 = local bus adapter, 5 = processor bus converter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * 6 = crossbar fabric connect, 7 = fabric interconnect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * 8 to 254 reserved, 255 = unknown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Bit 8 to 15 - DVI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * Bit 16 to 23 - IOC functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * Bit 24 to 39 - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Bit 40 to 63 - mod_pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * number of 4K pages a module occupies starting at conf_base_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define PAT_GET_ENTITY(value) (((value) >> 56) & 0xffUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define PAT_GET_DVI(value) (((value) >> 48) & 0xffUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define PAT_GET_IOC(value) (((value) >> 40) & 0xffUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define PAT_GET_MOD_PAGES(value) ((value) & 0xffffffUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ** PDC_PAT_CELL_GET_INFO return block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) typedef struct pdc_pat_cell_info_rtn_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned long pdc_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned long capabilities; /* see PDC_PAT_CAPABILITY_BIT_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned long reserved0[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned long cell_info; /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned long cell_phys_location;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned long cpu_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned long cpu_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned long io_chassis_phys_location;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned long cell_io_information;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned long reserved1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned long io_slot_info_size; /* 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned long header, info0, info1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned long phys_loc, hw_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) } io_slot[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned long cell_mem_size; /* 0x2e8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned long cell_dimm_info_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned long dimm_info[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned long fabric_info_size; /* 0x3f8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct { /* 0x380 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned long fabric_info_xbc_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned long rc_attached_to_xbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) } xbc[8*4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) } pdc_pat_cell_info_rtn_block_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* FIXME: mod[508] should really be a union of the various mod components */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct pdc_pat_cell_mod_maddr_block { /* PDC_PAT_CELL_MODULE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned long cba; /* func 0 cfg space address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned long mod_info; /* module information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned long mod_location; /* physical location of the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct hardware_path mod_path; /* module path (device path - layers) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned long mod[508]; /* PAT cell module components */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } __attribute__((aligned(8))) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) typedef struct pdc_pat_cell_mod_maddr_block pdc_pat_cell_mod_maddr_block_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) extern int pdc_pat_chassis_send_log(unsigned long status, unsigned long data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) extern int pdc_pat_cell_get_number(struct pdc_pat_cell_num *cell_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) extern int pdc_pat_cell_info(struct pdc_pat_cell_info_rtn_block *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned long *actcnt, unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned long cell_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) extern int pdc_pat_cell_module(unsigned long *actcnt, unsigned long ploc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned long mod, unsigned long view_type, void *mem_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) extern int pdc_pat_cell_num_to_loc(void *, unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) extern int pdc_pat_cpu_get_number(struct pdc_pat_cpu_num *cpu_info, unsigned long hpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) extern int pdc_pat_pd_get_addr_map(unsigned long *actual_len, void *mem_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned long count, unsigned long offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) extern int pdc_pat_pd_get_pdc_revisions(unsigned long *legacy_rev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned long *pat_rev, unsigned long *pdc_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) extern int pdc_pat_io_pci_cfg_read(unsigned long pci_addr, int pci_size, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) extern int pdc_pat_io_pci_cfg_write(unsigned long pci_addr, int pci_size, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) extern int pdc_pat_mem_pdt_info(struct pdc_pat_mem_retinfo *rinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) extern int pdc_pat_mem_pdt_cell_info(struct pdc_pat_mem_cell_pdt_retinfo *rinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned long cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) extern int pdc_pat_mem_read_cell_pdt(struct pdc_pat_mem_read_pd_retinfo *pret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned long *pdt_entries_ptr, unsigned long max_entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) extern int pdc_pat_mem_read_pd_pdt(struct pdc_pat_mem_read_pd_retinfo *pret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned long *pdt_entries_ptr, unsigned long count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned long offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) extern int pdc_pat_mem_get_dimm_phys_location(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct pdc_pat_mem_phys_mem_location *pret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned long phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #endif /* ! __PARISC_PATPDC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags