^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ASM_PARISC_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ASM_PARISC_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) ** HP PCI platforms generally support multiple bus adapters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) ** (workstations 1-~4, servers 2-~32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ** Newer platforms number the busses across PCI bus adapters *sparsely*.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ** E.g. 0, 8, 16, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ** Under a PCI bus, most HP platforms support PPBs up to two or three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ** levels deep. See "Bit3" product line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCI_MAX_BUSSES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* To be used as: mdelay(pci_post_reset_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * post_reset is the time the kernel should stall to prevent anyone from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * accessing the PCI bus once #RESET is de-asserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * PCI spec somewhere says 1 second but with multi-PCI bus systems,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * this makes the boot time much longer than necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * 20ms seems to work for all the HP PCI implementations to date.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define pci_post_reset_delay 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ** pci_hba_data (aka H2P_OBJECT in HP/UX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ** This is the "common" or "base" data structure which HBA drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ** (eg Dino or LBA) are required to place at the top of their own
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ** platform_data structure. I've heard this called "C inheritance" too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ** Data needed by pcibios layer belongs here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct pci_hba_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void __iomem *base_addr; /* aka Host Physical Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) const struct parisc_device *dev; /* device from PA bus walk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct pci_bus *hba_bus; /* primary PCI bus below HBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int hba_num; /* I/O port space access "key" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct resource bus_num; /* PCI bus numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct resource io_space; /* PIOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct resource lmmio_space; /* bus addresses < 4Gb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct resource elmmio_space; /* additional bus addresses < 4Gb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct resource gmmio_space; /* bus addresses > 4Gb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* NOTE: Dino code assumes it can use *all* of the lmmio_space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * elmmio_space and gmmio_space as a contiguous array of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * resources. This #define represents the array size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DINO_MAX_LMMIO_RESOURCES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned long lmmio_space_offset; /* CPU view - PCI view */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct ioc *iommu; /* IOMMU this device is under */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* REVISIT - spinlock to protect resources? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HBA_NAME_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) char io_name[HBA_NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) char lmmio_name[HBA_NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) char elmmio_name[HBA_NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) char gmmio_name[HBA_NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ** We support 2^16 I/O ports per HBA. These are set up in the form
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ** space address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define HBA_PORT_SPACE_BITS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCI_F_EXTEND 0xffffffff00000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #else /* !CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCI_F_EXTEND 0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #endif /* !CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ** Most PCI devices (eg Tulip, NCR720) also export the same registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ** to both MMIO and I/O port space. Due to poor performance of I/O Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ** access under HP PCI bus adapters, strongly recommend the use of MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ** address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ** While I'm at it more PA programming notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ** 1) MMIO stores (writes) are posted operations. This means the processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ** gets an "ACK" before the write actually gets to the device. A read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ** to the same device (or typically the bus adapter above it) will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ** force in-flight write transaction(s) out to the targeted device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ** before the read can complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ** respect to DMA on all platforms. Ie PIO data can reach the processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ** before in-flight DMA reaches memory. Since most SMP PA platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ** are I/O coherent, it generally doesn't matter...but sometimes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ** it does.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ** I've helped device driver writers debug both types of problems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct pci_port_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 (*inb) (struct pci_hba_data *hba, u16 port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u16 (*inw) (struct pci_hba_data *hba, u16 port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 (*inl) (struct pci_hba_data *hba, u16 port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void (*outb) (struct pci_hba_data *hba, u16 port, u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void (*outw) (struct pci_hba_data *hba, u16 port, u16 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void (*outl) (struct pci_hba_data *hba, u16 port, u32 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct pci_bios_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) void (*init)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void (*fixup_bus)(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ** Stuff declared in arch/parisc/kernel/pci.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) extern struct pci_port_ops *pci_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) extern struct pci_bios_ops *pci_bios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) extern void pcibios_register_hba(struct pci_hba_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static inline void pcibios_register_hba(struct pci_hba_data *x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) extern void pcibios_init_bridge(struct pci_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * 0 == check if bridge is numbered before re-numbering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * We *should* set this to zero for "legacy" platforms and one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * for PAT platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * But legacy platforms also need to renumber the busses below a Host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Bus controller. Adding a 4-port Tulip card on the first PCI root
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * bus of a C200 resulted in the secondary bus being numbered as 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * The second PCI host bus controller's root bus had already been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * assigned bus number 1 by firmware and sysfs complained.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * Firmware isn't doing anything wrong here since each controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * is its own PCI domain. It's simpler and easier for us to renumber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * the busses rather than treat each Dino as a separate PCI domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Eventually, we may want to introduce PCI domains for Superdome or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * rp7420/8420 boxes and then revisit this issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define pcibios_assign_all_busses() (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PCIBIOS_MIN_IO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return channel ? 15 : 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HAVE_PCI_MMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ARCH_GENERIC_PCI_MMAP_RESOURCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #endif /* __ASM_PARISC_PCI_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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