Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef __PARISC_LDCW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define __PARISC_LDCW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifndef CONFIG_PA20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) /* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)    and GCC only guarantees 8-byte alignment for stack locals, we can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)    be assured of 16-byte alignment for atomic lock data even if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)    specify "__attribute ((aligned(16)))" in the type declaration.  So,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)    we use a struct containing an array of four ints for the atomic lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)    type and dynamically select the 16-byte aligned int from the array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)    for the semaphore.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define __PA_LDCW_ALIGNMENT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define __PA_LDCW_ALIGN_ORDER	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define __ldcw_align(a) ({					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	unsigned long __ret = (unsigned long) &(a)->lock[0];	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	__ret = (__ret + __PA_LDCW_ALIGNMENT - 1)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		& ~(__PA_LDCW_ALIGNMENT - 1);			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	(volatile unsigned int *) __ret;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define __LDCW	"ldcw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #else /*CONFIG_PA20*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* From: "Jim Hull" <jim.hull of hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)    I've attached a summary of the change, but basically, for PA 2.0, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)    long as the ",CO" (coherent operation) completer is specified, then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)    16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)    they only require "natural" alignment (4-byte for ldcw, 8-byte for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)    ldcd). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define __PA_LDCW_ALIGNMENT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define __PA_LDCW_ALIGN_ORDER	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define __ldcw_align(a) (&(a)->slock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define __LDCW	"ldcw,co"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif /*!CONFIG_PA20*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)    We don't explicitly expose that "*a" may be written as reload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)    fails to find a register in class R1_REGS when "a" needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)    reloaded when generating 64-bit PIC code.  Instead, we clobber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)    memory to indicate to the compiler that the assembly code reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)    or writes to items other than those listed in the input and output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)    operands.  This may pessimize the code somewhat but __ldcw is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)    usually used within code blocks surrounded by memory barriers.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define __ldcw(a) ({						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	unsigned __ret;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	__asm__ __volatile__(__LDCW " 0(%1),%0"			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		: "=r" (__ret) : "r" (a) : "memory");		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	__ret;							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) # define __lock_aligned __section(".data..lock_aligned")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif /* __PARISC_LDCW_H */