^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _PARISC_HARDWARE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _PARISC_HARDWARE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define HWTYPE_ANY_ID PA_HWTYPE_ANY_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define HVERSION_ANY_ID PA_HVERSION_ANY_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define HVERSION_REV_ANY_ID PA_HVERSION_REV_ANY_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define SVERSION_ANY_ID PA_SVERSION_ANY_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct hp_hardware {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) unsigned short hw_type:5; /* HPHW_xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) unsigned short hversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) unsigned long sversion:28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) unsigned short opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) const char name[80]; /* The hardware description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct parisc_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) enum cpu_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) pcx = 0, /* pa7000 pa 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) pcxs = 1, /* pa7000 pa 1.1a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) pcxt = 2, /* pa7100 pa 1.1b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) pcxt_ = 3, /* pa7200 (t') pa 1.1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) pcxl = 4, /* pa7100lc pa 1.1d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) pcxl2 = 5, /* pa7300lc pa 1.1e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) pcxu = 6, /* pa8000 pa 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) pcxu_ = 7, /* pa8200 (u+) pa 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) pcxw = 8, /* pa8500 pa 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) pcxw_ = 9, /* pa8600 (w+) pa 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) pcxw2 = 10, /* pa8700 pa 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) mako = 11, /* pa8800 pa 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) mako2 = 12 /* pa8900 pa 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) extern const char * const cpu_name_version[][2]; /* mapping from enum cpu_type to strings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct parisc_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct io_module {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) volatile uint32_t nothing; /* reg 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) volatile uint32_t io_eim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) volatile uint32_t io_dc_adata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) volatile uint32_t io_ii_cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) volatile uint32_t io_dma_link; /* reg 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) volatile uint32_t io_dma_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) volatile uint32_t io_dma_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) volatile uint32_t io_dma_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) volatile uint32_t io_flex; /* reg 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) volatile uint32_t io_spa_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) volatile uint32_t reserved1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) volatile uint32_t io_command; /* reg 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) volatile uint32_t io_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) volatile uint32_t io_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) volatile uint32_t io_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) volatile uint32_t reserved2; /* reg 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) volatile uint32_t chain_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) volatile uint32_t sub_mask_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) volatile uint32_t reserved3[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) volatile uint32_t undefined[480];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) volatile uint32_t unpriv[512];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct bc_module {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) volatile uint32_t unused1[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) volatile uint32_t io_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) volatile uint32_t io_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) volatile uint32_t io_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) volatile uint32_t unused2[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) volatile uint32_t io_err_resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) volatile uint32_t io_err_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) volatile uint32_t io_err_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) volatile uint32_t unused3[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) volatile uint32_t io_io_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) volatile uint32_t io_io_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HPHW_NPROC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HPHW_MEMORY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define HPHW_B_DMA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HPHW_OBSOLETE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HPHW_A_DMA 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HPHW_A_DIRECT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HPHW_OTHER 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HPHW_BCPORT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HPHW_CIO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HPHW_CONSOLE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HPHW_FIO 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HPHW_BA 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HPHW_IOA 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HPHW_BRIDGE 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HPHW_FABRIC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HPHW_MC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HPHW_FAULTY 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct parisc_device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* hardware.c: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) extern const char *parisc_hardware_description(struct parisc_device_id *id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) extern enum cpu_type parisc_get_cpu_type(unsigned long hversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct hardware_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* drivers.c: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) extern struct parisc_device *alloc_pa_dev(unsigned long hpa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct hardware_path *path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) extern int register_parisc_device(struct parisc_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) extern int register_parisc_driver(struct parisc_driver *driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) extern int count_parisc_driver(struct parisc_driver *driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) extern int unregister_parisc_driver(struct parisc_driver *driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) extern void walk_central_bus(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) extern const struct parisc_device *find_pa_parent_type(const struct parisc_device *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) extern void print_parisc_devices(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) extern char *print_pa_hwpath(struct parisc_device *dev, char *path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) extern char *print_pci_hwpath(struct pci_dev *dev, char *path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) extern void get_pci_node_path(struct pci_dev *dev, struct hardware_path *path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) extern void init_parisc_bus(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) extern struct device *hwpath_to_device(struct hardware_path *modpath);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) extern void device_to_hwpath(struct device *dev, struct hardware_path *path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) extern int machine_has_merced_bus(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* inventory.c: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) extern void do_memory_inventory(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) extern void do_device_inventory(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif /* _PARISC_HARDWARE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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