^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* asm/dma.h: Defines for using and allocating dma channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Written by Hennus Bergman, 1992.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * High DMA channel support & info by Hannu Savolainen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * and John Boyd, Nov. 1992.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (c) Copyright 2000, Grant Grundler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _ASM_DMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _ASM_DMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/io.h> /* need byte IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define dma_outb outb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define dma_inb inb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ** (or rather not merge) DMAs into manageable chunks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ** On parisc, this is more of the software/tuning constraint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ** rather than the HW. I/O MMU allocation algorithms can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ** faster with smaller sizes (to some degree).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DMA_CHUNK_SIZE (BITS_PER_LONG*PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* The maximum address that we can perform a DMA transfer to on this platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ** New dynamic DMA interfaces should obsolete this....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MAX_DMA_ADDRESS (~0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ** We don't have DMA channels... well V-class does but the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ** Dynamic DMA Mapping interface will support them... right? :^)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ** Note: this is not relevant right now for PA-RISC, but we cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ** leave this as undefined because some things (e.g. sound)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ** won't compile :-(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MAX_DMA_CHANNELS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DMA_AUTOINIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* 8237 DMA controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* DMA controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DMA1_CMD_REG 0x08 /* command register (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DMA1_STAT_REG 0x08 /* status register (r) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DMA1_REQ_REG 0x09 /* request register (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DMA1_MODE_REG 0x0B /* mode register (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DMA2_CMD_REG 0xD0 /* command register (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DMA2_STAT_REG 0xD0 /* status register (r) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DMA2_REQ_REG 0xD2 /* request register (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DMA2_MODE_REG 0xD6 /* mode register (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static __inline__ unsigned long claim_dma_lock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static __inline__ void release_dma_lock(unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Get DMA residue count. After a DMA transfer, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * should return zero. Reading this while a DMA transfer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * still in progress will return unpredictable results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * If called before the channel has been used, it may return 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Otherwise, it returns the number of _bytes_ left to transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Assumes DMA flip-flop is clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static __inline__ int get_dma_residue(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* using short to get 16-bit wrap around */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned short count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) count = 1 + dma_inb(io_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) count += dma_inb(io_port) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return (dmanr<=3)? count : (count<<1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* enable/disable a specific DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static __inline__ void enable_dma(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #ifdef CONFIG_SUPERIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (dmanr<=3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dma_outb(dmanr, DMA1_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dma_outb(dmanr & 3, DMA2_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static __inline__ void disable_dma(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #ifdef CONFIG_SUPERIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (dmanr<=3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dma_outb(dmanr | 4, DMA1_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* reserve a DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define request_dma(dmanr, device_id) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Clear the 'DMA Pointer Flip Flop'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Write 0 for LSB/MSB, 1 for MSB/LSB access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Use this once to initialize the FF to a known state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * After that, keep track of it. :-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * --- In order to do that, the DMA routines below should ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * --- only be used while holding the DMA lock ! ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static __inline__ void clear_dma_ff(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* set mode (above) for a specific DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Set only the page register bits of the transfer address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * This is used for successive transfers when we know the contents of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * the lower 16 bits of the DMA current address register, but a 64k boundary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * may have been crossed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Set transfer address & page bits for specific DMA channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Assumes dma flipflop is clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * a specific DMA channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * You must ensure the parameters are valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * NOTE: from a manual: "the number of transfers is one more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * than the initial word count"! This is taken into account.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Assumes dma flip-flop is clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define free_dma(dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) extern int isa_dma_bridge_buggy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define isa_dma_bridge_buggy (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #endif /* _ASM_DMA_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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