^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _PARISC_DMA_MAPPING_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _PARISC_DMA_MAPPING_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) ** We need to support 4 different coherent dma models with one binary:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) ** I/O MMU consistent method dma_sync behavior
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) ** ============= ====================== =======================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) ** a) PA-7x00LC uncachable host memory flush/purge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) ** b) U2/Uturn cachable host memory NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) ** c) Ike/Astro cachable host memory NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ** d) EPIC/SAGA memory on EPIC/SAGA flush/reset DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ** PA-7[13]00LC processors have a GSC bus interface and no I/O MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ** Systems (eg PCX-T workstations) that don't fall into the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ** categories will need to modify the needed drivers to perform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ** flush/purge and allocate "regular" cacheable pages for everything.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) extern const struct dma_map_ops *hppa_dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) return hppa_dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #endif