Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * include/asm-parisc/cache.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __ARCH_PARISC_CACHE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __ARCH_PARISC_CACHE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <asm/alternative.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * have 32-byte cachelines.  The L1 length appears to be 16 bytes but this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * is not clearly documented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define L1_CACHE_BYTES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define L1_CACHE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SMP_CACHE_BYTES L1_CACHE_BYTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define __read_mostly __section(".data..read_mostly")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void parisc_cache_init(void);	/* initializes cache-flushing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) void disable_sr_hashing_asm(int); /* low level support for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void disable_sr_hashing(void);   /* turns off space register hashing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void free_sid(unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned long alloc_sid(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct seq_file;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) extern void show_cache_info(struct seq_file *m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) extern int split_tlb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) extern int dcache_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) extern int icache_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) extern struct pdc_cache_info cache_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void parisc_setup_cache_timing(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define pdtlb(addr)	asm volatile("pdtlb 0(%%sr1,%0)" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 			: : "r" (addr) : "memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define pitlb(addr)	asm volatile("pitlb 0(%%sr1,%0)" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			: : "r" (addr) : "memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define pdtlb_kernel(addr)  asm volatile("pdtlb 0(%0)"   \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			: : "r" (addr) : "memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 			ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 			: : "r" (addr) : "memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define asm_io_sync()	asm volatile("sync" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 			ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :::"memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif /* ! __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Classes of processor wrt: disabling space register hashing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SRHASH_PCXST    0   /* pcxs, pcxt, pcxt_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SRHASH_PCXL     1   /* pcxl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SRHASH_PA20     2   /* pcxu, pcxu_, pcxw, pcxw_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif