Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 1999 SuSE GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef _PARISC_ASSEMBLY_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define _PARISC_ASSEMBLY_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define CALLEE_FLOAT_FRAME_SIZE	80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define LDREG	ldd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define STREG	std
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define LDREGX  ldd,s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define LDREGM	ldd,mb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define STREGM	std,ma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SHRREG	shrd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SHLREG	shld
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define ANDCM   andcm,*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define	COND(x)	* ## x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define RP_OFFSET	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define FRAME_SIZE	128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CALLEE_REG_FRAME_SIZE	144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define REG_SZ		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define ASM_ULONG_INSN	.dword
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #else	/* CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define LDREG	ldw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define STREG	stw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LDREGX  ldwx,s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define LDREGM	ldwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define STREGM	stwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SHRREG	shr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SHLREG	shlw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ANDCM   andcm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define COND(x)	x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define RP_OFFSET	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define FRAME_SIZE	64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CALLEE_REG_FRAME_SIZE	128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define REG_SZ		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ASM_ULONG_INSN	.word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #ifdef CONFIG_PA20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define LDCW		ldcw,co
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define BL		b,l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) # ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #  define PA_ASM_LEVEL	2.0w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) # else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #  define PA_ASM_LEVEL	2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) # endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define LDCW		ldcw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define BL		bl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PA_ASM_LEVEL	1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #ifdef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * work around that for now... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.level 2.0w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #include <asm/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #include <asm/asmregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	sp	=	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	gp	=	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	ipsw	=	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 * We provide two versions of each macro to convert from physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	 * to virtual and vice versa. The "_r1" versions take one argument
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	 * register, but trashes r1 to do the conversion. The other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	 * version takes two arguments: a src and destination register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 * However, the source and destination registers can not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * the same register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.macro  tophys  grvirt, grphys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	ldil    L%(__PAGE_OFFSET), \grphys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	sub     \grvirt, \grphys, \grphys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.macro  tovirt  grphys, grvirt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	ldil    L%(__PAGE_OFFSET), \grvirt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	add     \grphys, \grvirt, \grvirt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.macro  tophys_r1  gr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	ldil    L%(__PAGE_OFFSET), %r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	sub     \gr, %r1, \gr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.macro  tovirt_r1  gr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	ldil    L%(__PAGE_OFFSET), %r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	add     \gr, %r1, \gr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.macro delay value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ldil	L%\value, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	ldo	R%\value(1), 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	addib,UV,n -1,1,.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	addib,NUV,n -1,1,.+8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.macro	debug value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.macro shlw r, sa, t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	zdep	\r, 31-(\sa), 32-(\sa), \t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* And the PA 2.0W shift left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.macro shld r, sa, t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	depd,z	\r, 63-(\sa), 64-(\sa), \t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* Shift Right - note the r and t can NOT be the same! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.macro shr r, sa, t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	extru \r, 31-(\sa), 32-(\sa), \t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* pa20w version of shift right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.macro shrd r, sa, t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	extrd,u \r, 63-(\sa), 64-(\sa), \t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/* load 32-bit 'value' into 'reg' compensating for the ldil
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 * sign-extension when running in wide mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 * WARNING!! neither 'value' nor 'reg' can be expressions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	 * containing '.'!!!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.macro	load32 value, reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	ldil	L%\value, \reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	ldo	R%\value(\reg), \reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.macro loadgp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ldil		L%__gp, %r27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	ldo		R%__gp(%r27), %r27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ldil		L%$global$, %r27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	ldo		R%$global$(%r27), %r27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.macro	save_general	regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	STREG %r1, PT_GR1 (\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	STREG %r2, PT_GR2 (\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	STREG %r3, PT_GR3 (\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	STREG %r4, PT_GR4 (\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	STREG %r5, PT_GR5 (\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	STREG %r6, PT_GR6 (\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	STREG %r7, PT_GR7 (\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	STREG %r8, PT_GR8 (\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	STREG %r9, PT_GR9 (\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	STREG %r10, PT_GR10(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	STREG %r11, PT_GR11(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	STREG %r12, PT_GR12(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	STREG %r13, PT_GR13(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	STREG %r14, PT_GR14(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	STREG %r15, PT_GR15(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	STREG %r16, PT_GR16(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	STREG %r17, PT_GR17(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	STREG %r18, PT_GR18(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	STREG %r19, PT_GR19(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	STREG %r20, PT_GR20(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	STREG %r21, PT_GR21(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	STREG %r22, PT_GR22(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	STREG %r23, PT_GR23(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	STREG %r24, PT_GR24(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	STREG %r25, PT_GR25(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* r26 is saved in get_stack and used to preserve a value across virt_map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	STREG %r27, PT_GR27(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	STREG %r28, PT_GR28(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* r29 is saved in get_stack and used to point to saved registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* r30 stack pointer saved in get_stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	STREG %r31, PT_GR31(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.macro	rest_general	regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* r1 used as a temp in rest_stack and is restored there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	LDREG PT_GR2 (\regs), %r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	LDREG PT_GR3 (\regs), %r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	LDREG PT_GR4 (\regs), %r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	LDREG PT_GR5 (\regs), %r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	LDREG PT_GR6 (\regs), %r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	LDREG PT_GR7 (\regs), %r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	LDREG PT_GR8 (\regs), %r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	LDREG PT_GR9 (\regs), %r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	LDREG PT_GR10(\regs), %r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	LDREG PT_GR11(\regs), %r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	LDREG PT_GR12(\regs), %r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	LDREG PT_GR13(\regs), %r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	LDREG PT_GR14(\regs), %r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	LDREG PT_GR15(\regs), %r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	LDREG PT_GR16(\regs), %r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	LDREG PT_GR17(\regs), %r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	LDREG PT_GR18(\regs), %r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	LDREG PT_GR19(\regs), %r19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	LDREG PT_GR20(\regs), %r20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	LDREG PT_GR21(\regs), %r21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	LDREG PT_GR22(\regs), %r22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	LDREG PT_GR23(\regs), %r23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	LDREG PT_GR24(\regs), %r24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	LDREG PT_GR25(\regs), %r25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	LDREG PT_GR26(\regs), %r26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	LDREG PT_GR27(\regs), %r27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	LDREG PT_GR28(\regs), %r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* r29 points to register save area, and is restored in rest_stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/* r30 stack pointer restored in rest_stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	LDREG PT_GR31(\regs), %r31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.macro	save_fp 	regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	fstd,ma  %fr0, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	fstd,ma	 %fr1, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	fstd,ma	 %fr2, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	fstd,ma	 %fr3, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	fstd,ma	 %fr4, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	fstd,ma	 %fr5, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	fstd,ma	 %fr6, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	fstd,ma	 %fr7, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	fstd,ma	 %fr8, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	fstd,ma	 %fr9, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	fstd,ma	%fr10, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	fstd,ma	%fr11, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	fstd,ma	%fr12, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	fstd,ma	%fr13, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	fstd,ma	%fr14, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	fstd,ma	%fr15, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	fstd,ma	%fr16, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	fstd,ma	%fr17, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	fstd,ma	%fr18, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	fstd,ma	%fr19, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	fstd,ma	%fr20, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	fstd,ma	%fr21, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	fstd,ma	%fr22, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	fstd,ma	%fr23, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	fstd,ma	%fr24, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	fstd,ma	%fr25, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	fstd,ma	%fr26, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	fstd,ma	%fr27, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	fstd,ma	%fr28, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	fstd,ma	%fr29, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	fstd,ma	%fr30, 8(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	fstd	%fr31, 0(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.macro	rest_fp 	regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	fldd	0(\regs),	 %fr31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	fldd,mb	-8(\regs),       %fr30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	fldd,mb	-8(\regs),       %fr29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	fldd,mb	-8(\regs),       %fr28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	fldd,mb	-8(\regs),       %fr27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	fldd,mb	-8(\regs),       %fr26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	fldd,mb	-8(\regs),       %fr25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	fldd,mb	-8(\regs),       %fr24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	fldd,mb	-8(\regs),       %fr23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	fldd,mb	-8(\regs),       %fr22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	fldd,mb	-8(\regs),       %fr21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	fldd,mb	-8(\regs),       %fr20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	fldd,mb	-8(\regs),       %fr19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	fldd,mb	-8(\regs),       %fr18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	fldd,mb	-8(\regs),       %fr17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	fldd,mb	-8(\regs),       %fr16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	fldd,mb	-8(\regs),       %fr15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	fldd,mb	-8(\regs),       %fr14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	fldd,mb	-8(\regs),       %fr13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	fldd,mb	-8(\regs),       %fr12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	fldd,mb	-8(\regs),       %fr11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	fldd,mb	-8(\regs),       %fr10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	fldd,mb	-8(\regs),       %fr9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	fldd,mb	-8(\regs),       %fr8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	fldd,mb	-8(\regs),       %fr7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	fldd,mb	-8(\regs),       %fr6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	fldd,mb	-8(\regs),       %fr5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	fldd,mb	-8(\regs),       %fr4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	fldd,mb	-8(\regs),       %fr3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	fldd,mb	-8(\regs),       %fr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	fldd,mb	-8(\regs),       %fr1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	fldd,mb	-8(\regs),       %fr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.macro	callee_save_float
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	fstd,ma	 %fr12,	8(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	fstd,ma	 %fr13,	8(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	fstd,ma	 %fr14,	8(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	fstd,ma	 %fr15,	8(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	fstd,ma	 %fr16,	8(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	fstd,ma	 %fr17,	8(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	fstd,ma	 %fr18,	8(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	fstd,ma	 %fr19,	8(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	fstd,ma	 %fr20,	8(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	fstd,ma	 %fr21,	8(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.macro	callee_rest_float
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	fldd,mb	-8(%r30),   %fr21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	fldd,mb	-8(%r30),   %fr20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	fldd,mb	-8(%r30),   %fr19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	fldd,mb	-8(%r30),   %fr18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	fldd,mb	-8(%r30),   %fr17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	fldd,mb	-8(%r30),   %fr16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	fldd,mb	-8(%r30),   %fr15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	fldd,mb	-8(%r30),   %fr14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	fldd,mb	-8(%r30),   %fr13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	fldd,mb	-8(%r30),   %fr12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.macro	callee_save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	std,ma	  %r3,	 CALLEE_REG_FRAME_SIZE(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	mfctl	  %cr27, %r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	std	  %r4,	-136(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	std	  %r5,	-128(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	std	  %r6,	-120(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	std	  %r7,	-112(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	std	  %r8,	-104(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	std	  %r9,	 -96(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	std	 %r10,	 -88(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	std	 %r11,	 -80(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	std	 %r12,	 -72(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	std	 %r13,	 -64(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	std	 %r14,	 -56(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	std	 %r15,	 -48(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	std	 %r16,	 -40(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	std	 %r17,	 -32(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	std	 %r18,	 -24(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	std	  %r3,	 -16(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.macro	callee_rest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	ldd	 -16(%r30),    %r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	ldd	 -24(%r30),   %r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	ldd	 -32(%r30),   %r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	ldd	 -40(%r30),   %r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	ldd	 -48(%r30),   %r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	ldd	 -56(%r30),   %r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	ldd	 -64(%r30),   %r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	ldd	 -72(%r30),   %r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	ldd	 -80(%r30),   %r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	ldd	 -88(%r30),   %r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	ldd	 -96(%r30),    %r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	ldd	-104(%r30),    %r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	ldd	-112(%r30),    %r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	ldd	-120(%r30),    %r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	ldd	-128(%r30),    %r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	ldd	-136(%r30),    %r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	mtctl	%r3, %cr27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	ldd,mb	-CALLEE_REG_FRAME_SIZE(%r30),    %r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #else /* ! CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	.macro	callee_save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	stw,ma	 %r3,	CALLEE_REG_FRAME_SIZE(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	mfctl	 %cr27, %r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	stw	 %r4,	-124(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	stw	 %r5,	-120(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	stw	 %r6,	-116(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	stw	 %r7,	-112(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	stw	 %r8,	-108(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	stw	 %r9,	-104(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	stw	 %r10,	-100(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	stw	 %r11,	 -96(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	stw	 %r12,	 -92(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	stw	 %r13,	 -88(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	stw	 %r14,	 -84(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	stw	 %r15,	 -80(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	stw	 %r16,	 -76(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	stw	 %r17,	 -72(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	stw	 %r18,	 -68(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	stw	  %r3,	 -64(%r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	.macro	callee_rest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	ldw	 -64(%r30),    %r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	ldw	 -68(%r30),   %r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	ldw	 -72(%r30),   %r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	ldw	 -76(%r30),   %r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	ldw	 -80(%r30),   %r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	ldw	 -84(%r30),   %r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	ldw	 -88(%r30),   %r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	ldw	 -92(%r30),   %r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	ldw	 -96(%r30),   %r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	ldw	-100(%r30),   %r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	ldw	-104(%r30),   %r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	ldw	-108(%r30),   %r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	ldw	-112(%r30),   %r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	ldw	-116(%r30),   %r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	ldw	-120(%r30),   %r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	ldw	-124(%r30),   %r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	mtctl	%r3, %cr27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	ldw,mb	-CALLEE_REG_FRAME_SIZE(%r30),   %r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #endif /* ! CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	.macro	save_specials	regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	SAVE_SP  (%sr0, PT_SR0 (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	SAVE_SP  (%sr1, PT_SR1 (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	SAVE_SP  (%sr2, PT_SR2 (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	SAVE_SP  (%sr3, PT_SR3 (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	SAVE_SP  (%sr4, PT_SR4 (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	SAVE_SP  (%sr5, PT_SR5 (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	SAVE_SP  (%sr6, PT_SR6 (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	SAVE_CR  (%cr17, PT_IASQ0(\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	mtctl	 %r0,	%cr17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	SAVE_CR  (%cr17, PT_IASQ1(\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	SAVE_CR  (%cr18, PT_IAOQ0(\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	mtctl	 %r0,	%cr18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	SAVE_CR  (%cr18, PT_IAOQ1(\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	/* cr11 (sar) is a funny one.  5 bits on PA1.1 and 6 bit on PA2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	 * reads 5 bits.  Use mfctl,w to read all six bits.  Otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	 * we lose the 6th bit on a save/restore over interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	mfctl,w  %cr11, %r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	STREG    %r1, PT_SAR (\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	SAVE_CR  (%cr11, PT_SAR  (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	SAVE_CR  (%cr19, PT_IIR  (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	 * Code immediately following this macro (in intr_save) relies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	 * on r8 containing ipsw.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	mfctl    %cr22, %r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	STREG    %r8,   PT_PSW(\regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	.macro	rest_specials	regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	REST_SP  (%sr0, PT_SR0 (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	REST_SP  (%sr1, PT_SR1 (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	REST_SP  (%sr2, PT_SR2 (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	REST_SP  (%sr3, PT_SR3 (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	REST_SP  (%sr4, PT_SR4 (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	REST_SP  (%sr5, PT_SR5 (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	REST_SP  (%sr6, PT_SR6 (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	REST_SP  (%sr7, PT_SR7 (\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	REST_CR	(%cr17, PT_IASQ0(\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	REST_CR	(%cr17, PT_IASQ1(\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	REST_CR	(%cr18, PT_IAOQ0(\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	REST_CR	(%cr18, PT_IAOQ1(\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	REST_CR (%cr11, PT_SAR	(\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	REST_CR	(%cr22, PT_PSW	(\regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	/* First step to create a "relied upon translation"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	 * See PA 2.0 Arch. page F-4 and F-5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	 * The ssm was originally necessary due to a "PCxT bug".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	 * But someone decided it needed to be added to the architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	 * It's been carried forward into PA 2.0 Arch as well. :^(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	 * rsm/ssm prevents the ifetch unit from speculatively fetching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	 * instructions past this line in the code stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	 * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	.macro	pcxt_ssm_bug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	rsm	PSW_SM_I,%r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	nop	/* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	nop	/* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	nop	/* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	nop	/* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	nop	/* 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	nop	/* 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	nop	/* 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	 * ASM_EXCEPTIONTABLE_ENTRY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	 * Creates an exception table entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	 * Do not convert to a assembler macro. This won't work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define ASM_EXCEPTIONTABLE_ENTRY(fault_addr, except_addr)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	.section __ex_table,"aw"			!	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	.word (fault_addr - .), (except_addr - .)	!	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	.previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #endif