^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OpenRISC tlb.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Linux architectural port borrowing liberally from similar works of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * others. All original copyrights apply as per the original source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * declaration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Modifications for the OpenRISC architecture:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2010-2011 Julius Baxter <julius.baxter@orsoc.se>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mman.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/spr_defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NO_CONTEXT -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NUM_DTLB_SETS (1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SPR_DMMUCFGR_NTS_OFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define NUM_ITLB_SETS (1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SPR_IMMUCFGR_NTS_OFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DTLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_DTLB_SETS-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ITLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_ITLB_SETS-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Invalidate all TLB entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * This comes down to setting the 'valid' bit for all xTLBMR registers to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Easiest way to accomplish this is to just zero out the xTLBMR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * completely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void local_flush_tlb_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long num_tlb_sets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Determine number of sets for IMMU. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* FIXME: Assumption is I & D nsets equal. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) num_tlb_sets = NUM_ITLB_SETS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) for (i = 0; i < num_tlb_sets; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mtspr_off(SPR_DTLBMR_BASE(0), i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mtspr_off(SPR_ITLBMR_BASE(0), i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define have_dtlbeir (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_TEIRI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define have_itlbeir (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_TEIRI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Invalidate a single page. This is what the xTLBEIR register is for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * There's no point in checking the vma for PAGE_EXEC to determine whether it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * the data or instruction TLB that should be flushed... that would take more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * than the few instructions that the following compiles down to!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * The case where we don't have the xTLBEIR register really only works for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * MMU's with a single way and is hard-coded that way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define flush_dtlb_page_eir(addr) mtspr(SPR_DTLBEIR, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define flush_dtlb_page_no_eir(addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mtspr_off(SPR_DTLBMR_BASE(0), DTLB_OFFSET(addr), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define flush_itlb_page_eir(addr) mtspr(SPR_ITLBEIR, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define flush_itlb_page_no_eir(addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mtspr_off(SPR_ITLBMR_BASE(0), ITLB_OFFSET(addr), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (have_dtlbeir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) flush_dtlb_page_eir(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) flush_dtlb_page_no_eir(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (have_itlbeir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) flush_itlb_page_eir(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) flush_itlb_page_no_eir(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void local_flush_tlb_range(struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) bool dtlbeir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bool itlbeir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dtlbeir = have_dtlbeir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) itlbeir = have_itlbeir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) for (addr = start; addr < end; addr += PAGE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (dtlbeir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) flush_dtlb_page_eir(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) flush_dtlb_page_no_eir(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (itlbeir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) flush_itlb_page_eir(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) flush_itlb_page_no_eir(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Invalidate the selected mm context only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * FIXME: Due to some bug here, we're flushing everything for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * This should be changed to loop over over mm and call flush_tlb_range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void local_flush_tlb_mm(struct mm_struct *mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Was seeing bugs with the mm struct passed to us. Scrapped most of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) this function. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Several architctures do this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) local_flush_tlb_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* called in schedule() just before actually doing the switch_to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) void switch_mm(struct mm_struct *prev, struct mm_struct *next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct task_struct *next_tsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (unlikely(prev == next))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) cpumask_clear_cpu(cpu, mm_cpumask(prev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) cpumask_set_cpu(cpu, mm_cpumask(next));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* remember the pgd for the fault handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * this is similar to the pgd register in some other CPU's.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * we need our own copy of it because current and active_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * might be invalid at points where we still need to derefer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * the pgd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) current_pgd[cpu] = next->pgd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* We don't have context support implemented, so flush all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * entries belonging to previous map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) local_flush_tlb_mm(prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Initialize the context related info for a new mm_struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mm->context = NO_CONTEXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* called by __exit_mm to destroy the used MMU context if any before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * destroying the mm itself. this is only called when the last user of the mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * drops it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void destroy_context(struct mm_struct *mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) flush_tlb_mm(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* called once during VM initialization, from init.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) void __init tlb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Do nothing... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* invalidate the entire TLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* flush_tlb_all(); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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