Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * OpenRISC setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Linux architectural port borrowing liberally from similar works of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * others.  All original copyrights apply as per the original source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * declaration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Modifications for the OpenRISC architecture:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * This file handles the architecture-dependent parts of initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/initrd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/of_fdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <asm/sections.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <asm/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <asm/cpuinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <asm/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #include "vmlinux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static void __init setup_memory(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	unsigned long ram_start_pfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	unsigned long ram_end_pfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	phys_addr_t memory_start, memory_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	memory_end = memory_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	/* Find main memory where is the kernel, we assume its the only one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	memory_start = memblock_start_of_DRAM();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	memory_end = memblock_end_of_DRAM();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	if (!memory_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		panic("No memory!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	ram_start_pfn = PFN_UP(memory_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	ram_end_pfn = PFN_DOWN(memblock_end_of_DRAM());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	/* setup bootmem globals (we use no_bootmem, but mm still depends on this) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	min_low_pfn = ram_start_pfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	max_low_pfn = ram_end_pfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	max_pfn = ram_end_pfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 * initialize the boot-time allocator (with low memory only).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 * This makes the memory from the end of the kernel to the end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 * RAM usable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	memblock_reserve(__pa(_stext), _end - _stext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #ifdef CONFIG_BLK_DEV_INITRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* Then reserve the initrd, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (initrd_start && (initrd_end > initrd_start)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		unsigned long aligned_start = ALIGN_DOWN(initrd_start, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		unsigned long aligned_end = ALIGN(initrd_end, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		memblock_reserve(__pa(aligned_start), aligned_end - aligned_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #endif /* CONFIG_BLK_DEV_INITRD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	early_init_fdt_reserve_self();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	early_init_fdt_scan_reserved_mem();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	memblock_dump_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static void print_cpuinfo(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	unsigned long upr = mfspr(SPR_UPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	unsigned long vr = mfspr(SPR_VR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	unsigned int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	unsigned int revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	version = (vr & SPR_VR_VER) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	revision = (vr & SPR_VR_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	printk(KERN_INFO "CPU: OpenRISC-%x (revision %d) @%d MHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	       version, revision, cpuinfo->clock_frequency / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (!(upr & SPR_UPR_UP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		       "-- no UPR register... unable to detect configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (upr & SPR_UPR_DCP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		       "-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		       cpuinfo->dcache_size, cpuinfo->dcache_block_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		       cpuinfo->dcache_ways);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		printk(KERN_INFO "-- dcache disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (upr & SPR_UPR_ICP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		       "-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		       cpuinfo->icache_size, cpuinfo->icache_block_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		       cpuinfo->icache_ways);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		printk(KERN_INFO "-- icache disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (upr & SPR_UPR_DMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		       1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		       1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (upr & SPR_UPR_IMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		printk(KERN_INFO "-- immu: %4d entries, %lu way(s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		       1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		       1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	printk(KERN_INFO "-- additional features:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (upr & SPR_UPR_DUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		printk(KERN_INFO "-- debug unit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (upr & SPR_UPR_PCUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		printk(KERN_INFO "-- performance counters\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (upr & SPR_UPR_PMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		printk(KERN_INFO "-- power management\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (upr & SPR_UPR_PICP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		printk(KERN_INFO "-- PIC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (upr & SPR_UPR_TTP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		printk(KERN_INFO "-- timer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (upr & SPR_UPR_CUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		printk(KERN_INFO "-- custom unit(s)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static struct device_node *setup_find_cpu_node(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	u32 hwid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct device_node *cpun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	for_each_of_cpu_node(cpun) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		if (of_property_read_u32(cpun, "reg", &hwid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		if (hwid == cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			return cpun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) void __init setup_cpuinfo(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct device_node *cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	unsigned long iccfgr, dccfgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	unsigned long cache_set_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	int cpu_id = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	cpu = setup_find_cpu_node(cpu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (!cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		panic("Couldn't find CPU%d in device tree...\n", cpu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	iccfgr = mfspr(SPR_ICCFGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	cpuinfo->icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	cpuinfo->icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	cpuinfo->icache_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	    cache_set_size * cpuinfo->icache_ways * cpuinfo->icache_block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	dccfgr = mfspr(SPR_DCCFGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	cpuinfo->dcache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	cpuinfo->dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	cpuinfo->dcache_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	    cache_set_size * cpuinfo->dcache_ways * cpuinfo->dcache_block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (of_property_read_u32(cpu, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				 &cpuinfo->clock_frequency)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		       "Device tree missing CPU 'clock-frequency' parameter."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		       "Assuming frequency 25MHZ"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		       "This is probably not what you want.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	cpuinfo->coreid = mfspr(SPR_COREID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	of_node_put(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	print_cpuinfo();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  * or32_early_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  * Handles the pointer to the device tree that this kernel is to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  * for establishing the available platform devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  * Falls back on built-in device tree in case null pointer is passed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) void __init or32_early_setup(void *fdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (fdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		pr_info("FDT at %p\n", fdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		fdt = __dtb_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		pr_info("Compiled-in FDT at %p\n", fdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	early_init_devtree(fdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static inline unsigned long extract_value_bits(unsigned long reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 					       short bit_nr, short width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	return (reg >> bit_nr) & (0 << width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static inline unsigned long extract_value(unsigned long reg, unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	while (!(mask & 0x1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		reg = reg >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		mask = mask >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	return mask & reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) void __init detect_unit_config(unsigned long upr, unsigned long mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			       char *text, void (*func) (void))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (text != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		printk("%s", text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (upr & mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		if (func != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			func();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			printk("present\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		printk("not present\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  * calibrate_delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  * Lightweight calibrate_delay implementation that calculates loops_per_jiffy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  * from the clock frequency passed in via the device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void calibrate_delay(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	const int *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	struct device_node *cpu = setup_find_cpu_node(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	val = of_get_property(cpu, "clock-frequency", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		panic("no cpu 'clock-frequency' parameter in device tree");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	loops_per_jiffy = *val / HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		loops_per_jiffy / (500000 / HZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		(loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	of_node_put(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) void __init setup_arch(char **cmdline_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	unflatten_and_copy_device_tree();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	setup_cpuinfo();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	smp_init_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	/* process 1's initial memory region is the kernel code/data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	init_mm.start_code = (unsigned long)_stext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	init_mm.end_code = (unsigned long)_etext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	init_mm.end_data = (unsigned long)_edata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	init_mm.brk = (unsigned long)_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #ifdef CONFIG_BLK_DEV_INITRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (initrd_start == initrd_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		printk(KERN_INFO "Initial ramdisk not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		initrd_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		initrd_end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		printk(KERN_INFO "Initial ramdisk at: 0x%p (%lu bytes)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		       (void *)(initrd_start), initrd_end - initrd_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		initrd_below_start_ok = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	/* setup memblock allocator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	setup_memory();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	/* paging_init() sets up the MMU and marks all pages as reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	paging_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	*cmdline_p = boot_command_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	printk(KERN_INFO "OpenRISC Linux -- http://openrisc.io\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int show_cpuinfo(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	unsigned int vr, cpucfgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	unsigned int avr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	unsigned int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	struct cpuinfo_or1k *cpuinfo = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	vr = mfspr(SPR_VR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	cpucfgr = mfspr(SPR_CPUCFGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	seq_printf(m, "processor\t\t: %d\n", cpuinfo->coreid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	if (vr & SPR_VR_UVRP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		vr = mfspr(SPR_VR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		version = vr & SPR_VR2_VER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		avr = mfspr(SPR_AVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		seq_printf(m, "cpu architecture\t: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			   "OpenRISC 1000 (%d.%d-rev%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 			   (avr >> 24) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			   (avr >> 16) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 			   (avr >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		seq_printf(m, "cpu implementation id\t: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			   (vr & SPR_VR2_CPUID) >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		seq_printf(m, "cpu version\t\t: 0x%x\n", version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		version = (vr & SPR_VR_VER) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		seq_printf(m, "cpu\t\t\t: OpenRISC-%x\n", version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	seq_printf(m, "dcache block size\t: %d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		   cpuinfo->dcache_block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache_ways);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	seq_printf(m, "icache block size\t: %d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		   cpuinfo->icache_block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache_ways);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		   1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		   1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	seq_printf(m, "dmmu\t\t\t: %d entries, %lu ways\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		   1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		   1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	seq_printf(m, "bogomips\t\t: %lu.%02lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		   (loops_per_jiffy * HZ) / 500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		   ((loops_per_jiffy * HZ) / 5000) % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	seq_puts(m, "features\t\t: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB32S ? "orbis32" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB64S ? "orbis64" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF32S ? "orfpx32" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF64S ? "orfpx64" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OV64S ? "orvdx64" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	seq_puts(m, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	seq_puts(m, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static void *c_start(struct seq_file *m, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	*pos = cpumask_next(*pos - 1, cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	if ((*pos) < nr_cpu_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		return &cpuinfo_or1k[*pos];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void *c_next(struct seq_file *m, void *v, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	(*pos)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	return c_start(m, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static void c_stop(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) const struct seq_operations cpuinfo_op = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	.start = c_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	.next = c_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	.stop = c_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	.show = show_cpuinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };