^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OpenRISC head.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Linux architectural port borrowing liberally from similar works of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * others. All original copyrights apply as per the original source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * declaration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Modifications for the OpenRISC architecture:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/threads.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/spr_defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of_fdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define tophys(rd,rs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) l.movhi rd,hi(-KERNELBASE) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) l.add rd,rd,rs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLEAR_GPR(gpr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) l.movhi gpr,0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LOAD_SYMBOL_2_GPR(gpr,symbol) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) l.movhi gpr,hi(symbol) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) l.ori gpr,gpr,lo(symbol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UART_BASE_ADD 0x90000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EXCEPTION_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_SM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SYSCALL_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_IEE | SPR_SR_TEE | SPR_SR_SM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* ============================================[ tmp store locations ]=== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPR_SHADOW_GPR(x) ((x) + SPR_GPR_BASE + 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * emergency_print temporary stores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EMERGENCY_PRINT_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EMERGENCY_PRINT_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EMERGENCY_PRINT_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EMERGENCY_PRINT_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define EMERGENCY_PRINT_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define EMERGENCY_PRINT_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EMERGENCY_PRINT_STORE_GPR7 l.mtspr r0,r7,SPR_SHADOW_GPR(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define EMERGENCY_PRINT_LOAD_GPR7 l.mfspr r7,r0,SPR_SHADOW_GPR(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EMERGENCY_PRINT_STORE_GPR8 l.mtspr r0,r8,SPR_SHADOW_GPR(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EMERGENCY_PRINT_LOAD_GPR8 l.mfspr r8,r0,SPR_SHADOW_GPR(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define EMERGENCY_PRINT_STORE_GPR9 l.mtspr r0,r9,SPR_SHADOW_GPR(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EMERGENCY_PRINT_LOAD_GPR9 l.mfspr r9,r0,SPR_SHADOW_GPR(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * TLB miss handlers temorary stores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define EXCEPTION_STORE_GPR2 l.mtspr r0,r2,SPR_SHADOW_GPR(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define EXCEPTION_LOAD_GPR2 l.mfspr r2,r0,SPR_SHADOW_GPR(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define EXCEPTION_STORE_GPR3 l.mtspr r0,r3,SPR_SHADOW_GPR(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define EXCEPTION_LOAD_GPR3 l.mfspr r3,r0,SPR_SHADOW_GPR(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define EXCEPTION_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define EXCEPTION_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define EXCEPTION_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define EXCEPTION_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define EXCEPTION_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define EXCEPTION_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * EXCEPTION_HANDLE temporary stores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define EXCEPTION_T_STORE_GPR30 l.mtspr r0,r30,SPR_SHADOW_GPR(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define EXCEPTION_T_LOAD_GPR30(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define EXCEPTION_T_STORE_GPR10 l.mtspr r0,r10,SPR_SHADOW_GPR(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define EXCEPTION_T_LOAD_GPR10(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define EXCEPTION_T_STORE_SP l.mtspr r0,r1,SPR_SHADOW_GPR(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define EXCEPTION_T_LOAD_SP(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* =========================================================[ macros ]=== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GET_CURRENT_PGD(reg,t1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) l.mfspr t1,r0,SPR_COREID ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) l.slli t1,t1,2 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) l.add reg,reg,t1 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) tophys (t1,reg) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) l.lwz reg,0(t1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GET_CURRENT_PGD(reg,t1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) tophys (t1,reg) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) l.lwz reg,0(t1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Load r10 from current_thread_info_set - clobbers r1 and r30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define GET_CURRENT_THREAD_INFO \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tophys (r30,r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) l.mfspr r10,r0,SPR_COREID ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) l.slli r10,r10,2 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) l.add r30,r30,r10 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* r10: current_thread_info */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) l.lwz r10,0(r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define GET_CURRENT_THREAD_INFO \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) tophys (r30,r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* r10: current_thread_info */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) l.lwz r10,0(r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * DSCR: this is a common hook for handling exceptions. it will save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * the needed registers, set up stack and pointer to current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * then jump to the handler while enabling MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * PRMS: handler - a function to jump to. it has to save the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * remaining registers to kernel stack, call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * appropriate arch-independant exception handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * and finaly jump to ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * PREQ: unchanged state from the time exception happened
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * POST: SAVED the following registers original value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * to the new created exception frame pointed to by r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * r1 - ksp pointing to the new (exception) frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * r4 - EEAR exception EA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * r10 - current pointing to current_thread_info struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * r12 - syscall 0, since we didn't come from syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * r30 - handler address of the handler we'll jump to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * handler has to save remaining registers to the exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * ksp frame *before* tainting them!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * NOTE: this function is not reentrant per se. reentrancy is guaranteed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * by processor disabling all exceptions/interrupts when exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * accours.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * OPTM: no need to make it so wasteful to extract ksp when in user mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define EXCEPTION_HANDLE(handler) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) EXCEPTION_T_STORE_GPR30 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) l.mfspr r30,r0,SPR_ESR_BASE ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) l.andi r30,r30,SPR_SR_SM ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) l.sfeqi r30,0 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) EXCEPTION_T_STORE_GPR10 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) l.bnf 2f /* kernel_mode */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) EXCEPTION_T_STORE_SP /* delay slot */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 1: /* user_mode: */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) GET_CURRENT_THREAD_INFO ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) tophys (r30,r10) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) l.lwz r1,(TI_KSP)(r30) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* fall through */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 2: /* kernel_mode: */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* create new stack frame, save only needed gprs */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* r1: KSP, r10: current, r4: EEAR, r31: __pa(KSP) */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* r12: temp, syscall indicator */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) l.addi r1,r1,-(INT_FRAME_SIZE) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* r1 is KSP, r30 is __pa(KSP) */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) tophys (r30,r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) l.sw PT_GPR12(r30),r12 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* r4 use for tmp before EA */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) l.mfspr r12,r0,SPR_EPCR_BASE ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) l.sw PT_PC(r30),r12 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) l.mfspr r12,r0,SPR_ESR_BASE ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) l.sw PT_SR(r30),r12 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* save r30 */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) EXCEPTION_T_LOAD_GPR30(r12) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) l.sw PT_GPR30(r30),r12 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* save r10 as was prior to exception */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) EXCEPTION_T_LOAD_GPR10(r12) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) l.sw PT_GPR10(r30),r12 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* save PT_SP as was prior to exception */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) EXCEPTION_T_LOAD_SP(r12) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) l.sw PT_SP(r30),r12 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* save exception r4, set r4 = EA */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) l.sw PT_GPR4(r30),r4 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) l.mfspr r4,r0,SPR_EEAR_BASE ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* r12 == 1 if we come from syscall */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) CLEAR_GPR(r12) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* ----- turn on MMU ----- */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Carry DSX into exception SR */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) l.mfspr r30,r0,SPR_SR ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) l.andi r30,r30,SPR_SR_DSX ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) l.ori r30,r30,(EXCEPTION_SR) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) l.mtspr r0,r30,SPR_ESR_BASE ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* r30: EA address of handler */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) LOAD_SYMBOL_2_GPR(r30,handler) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) l.mtspr r0,r30,SPR_EPCR_BASE ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) l.rfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * this doesn't work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * #ifdef CONFIG_JUMP_UPON_UNHANDLED_EXCEPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * #define UNHANDLED_EXCEPTION(handler) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * l.ori r3,r0,0x1 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * l.mtspr r0,r3,SPR_SR ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * l.movhi r3,hi(0xf0000100) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * l.ori r3,r3,lo(0xf0000100) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * l.jr r3 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * l.nop 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* DSCR: this is the same as EXCEPTION_HANDLE(), we are just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * a bit more carefull (if we have a PT_SP or current pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * corruption) and set them up from 'current_set'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define UNHANDLED_EXCEPTION(handler) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) EXCEPTION_T_STORE_GPR30 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) EXCEPTION_T_STORE_GPR10 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) EXCEPTION_T_STORE_SP ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* temporary store r3, r9 into r1, r10 */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) l.addi r1,r3,0x0 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) l.addi r10,r9,0x0 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* the string referenced by r3 must be low enough */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) l.jal _emergency_print ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) l.ori r3,r0,lo(_string_unhandled_exception) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) l.mfspr r3,r0,SPR_NPC ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) l.jal _emergency_print_nr ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) l.andi r3,r3,0x1f00 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* the string referenced by r3 must be low enough */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) l.jal _emergency_print ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) l.ori r3,r0,lo(_string_epc_prefix) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) l.jal _emergency_print_nr ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) l.mfspr r3,r0,SPR_EPCR_BASE ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) l.jal _emergency_print ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) l.ori r3,r0,lo(_string_nl) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* end of printing */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) l.addi r3,r1,0x0 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) l.addi r9,r10,0x0 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* extract current, ksp from current_set */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) LOAD_SYMBOL_2_GPR(r1,_unhandled_stack_top) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) LOAD_SYMBOL_2_GPR(r10,init_thread_union) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* create new stack frame, save only needed gprs */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* r1: KSP, r10: current, r31: __pa(KSP) */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* r12: temp, syscall indicator, r13 temp */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) l.addi r1,r1,-(INT_FRAME_SIZE) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* r1 is KSP, r30 is __pa(KSP) */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) tophys (r30,r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) l.sw PT_GPR12(r30),r12 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) l.mfspr r12,r0,SPR_EPCR_BASE ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) l.sw PT_PC(r30),r12 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) l.mfspr r12,r0,SPR_ESR_BASE ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) l.sw PT_SR(r30),r12 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* save r31 */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) EXCEPTION_T_LOAD_GPR30(r12) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) l.sw PT_GPR30(r30),r12 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* save r10 as was prior to exception */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) EXCEPTION_T_LOAD_GPR10(r12) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) l.sw PT_GPR10(r30),r12 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* save PT_SP as was prior to exception */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) EXCEPTION_T_LOAD_SP(r12) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) l.sw PT_SP(r30),r12 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) l.sw PT_GPR13(r30),r13 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* --> */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* save exception r4, set r4 = EA */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) l.sw PT_GPR4(r30),r4 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) l.mfspr r4,r0,SPR_EEAR_BASE ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* r12 == 1 if we come from syscall */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) CLEAR_GPR(r12) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* ----- play a MMU trick ----- */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) l.ori r30,r0,(EXCEPTION_SR) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) l.mtspr r0,r30,SPR_ESR_BASE ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* r31: EA address of handler */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) LOAD_SYMBOL_2_GPR(r30,handler) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) l.mtspr r0,r30,SPR_EPCR_BASE ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) l.rfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* =====================================================[ exceptions] === */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* ---[ 0x100: RESET exception ]----------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .org 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Jump to .init code at _start which lives in the .head section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * and will be discarded after boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) LOAD_SYMBOL_2_GPR(r15, _start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) tophys (r13,r15) /* MMU disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) l.jr r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* ---[ 0x200: BUS exception ]------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .org 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) _dispatch_bus_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) EXCEPTION_HANDLE(_bus_fault_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .org 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) _dispatch_do_dpage_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) // totaly disable timer interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) // l.mtspr r0,r0,SPR_TTMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) // DEBUG_TLB_PROBE(0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) // EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) EXCEPTION_HANDLE(_data_page_fault_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .org 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) _dispatch_do_ipage_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) // totaly disable timer interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) // l.mtspr r0,r0,SPR_TTMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) // DEBUG_TLB_PROBE(0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) // EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) EXCEPTION_HANDLE(_insn_page_fault_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* ---[ 0x500: Timer exception ]----------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .org 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) EXCEPTION_HANDLE(_timer_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* ---[ 0x600: Alignment exception ]-------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .org 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) EXCEPTION_HANDLE(_alignment_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .org 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) EXCEPTION_HANDLE(_illegal_instruction_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* ---[ 0x800: External interrupt exception ]---------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .org 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) EXCEPTION_HANDLE(_external_irq_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .org 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) l.j boot_dtlb_miss_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .org 0xa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) l.j boot_itlb_miss_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* ---[ 0xb00: Range exception ]----------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .org 0xb00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) UNHANDLED_EXCEPTION(_vector_0xb00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .org 0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) EXCEPTION_HANDLE(_sys_call_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* ---[ 0xd00: Trap exception ]------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .org 0xd00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) UNHANDLED_EXCEPTION(_vector_0xd00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* ---[ 0xe00: Trap exception ]------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .org 0xe00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) // UNHANDLED_EXCEPTION(_vector_0xe00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) EXCEPTION_HANDLE(_trap_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .org 0xf00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) UNHANDLED_EXCEPTION(_vector_0xf00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* ---[ 0x1000: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .org 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) UNHANDLED_EXCEPTION(_vector_0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* ---[ 0x1100: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .org 0x1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) UNHANDLED_EXCEPTION(_vector_0x1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* ---[ 0x1200: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .org 0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) UNHANDLED_EXCEPTION(_vector_0x1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* ---[ 0x1300: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .org 0x1300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) UNHANDLED_EXCEPTION(_vector_0x1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* ---[ 0x1400: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .org 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) UNHANDLED_EXCEPTION(_vector_0x1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* ---[ 0x1500: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .org 0x1500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) UNHANDLED_EXCEPTION(_vector_0x1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* ---[ 0x1600: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .org 0x1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) UNHANDLED_EXCEPTION(_vector_0x1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* ---[ 0x1700: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .org 0x1700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) UNHANDLED_EXCEPTION(_vector_0x1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* ---[ 0x1800: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .org 0x1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) UNHANDLED_EXCEPTION(_vector_0x1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* ---[ 0x1900: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .org 0x1900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) UNHANDLED_EXCEPTION(_vector_0x1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .org 0x1a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) UNHANDLED_EXCEPTION(_vector_0x1a00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .org 0x1b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) UNHANDLED_EXCEPTION(_vector_0x1b00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .org 0x1c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) UNHANDLED_EXCEPTION(_vector_0x1c00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .org 0x1d00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) UNHANDLED_EXCEPTION(_vector_0x1d00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .org 0x1e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) UNHANDLED_EXCEPTION(_vector_0x1e00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .org 0x1f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) UNHANDLED_EXCEPTION(_vector_0x1f00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .org 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* ===================================================[ kernel start ]=== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* .text*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* This early stuff belongs in HEAD, but some of the functions below definitely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * don't... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) __HEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .global _start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) _start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Init r0 to zero as per spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) CLEAR_GPR(r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* save kernel parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) l.or r25,r0,r3 /* pointer to fdt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * ensure a deterministic start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) l.ori r3,r0,0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) l.mtspr r0,r3,SPR_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) CLEAR_GPR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) CLEAR_GPR(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) CLEAR_GPR(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) CLEAR_GPR(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) CLEAR_GPR(r5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) CLEAR_GPR(r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) CLEAR_GPR(r7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) CLEAR_GPR(r8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) CLEAR_GPR(r9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) CLEAR_GPR(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) CLEAR_GPR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) CLEAR_GPR(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) CLEAR_GPR(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) CLEAR_GPR(r14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) CLEAR_GPR(r15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) CLEAR_GPR(r16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) CLEAR_GPR(r17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) CLEAR_GPR(r18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) CLEAR_GPR(r19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) CLEAR_GPR(r20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) CLEAR_GPR(r21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) CLEAR_GPR(r22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) CLEAR_GPR(r23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) CLEAR_GPR(r24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) CLEAR_GPR(r26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) CLEAR_GPR(r27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) CLEAR_GPR(r28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) CLEAR_GPR(r29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) CLEAR_GPR(r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) CLEAR_GPR(r31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) l.mfspr r26,r0,SPR_COREID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) l.sfeq r26,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) l.bnf secondary_wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * set up initial ksp and current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* setup kernel stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) LOAD_SYMBOL_2_GPR(r1,init_thread_union + THREAD_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) LOAD_SYMBOL_2_GPR(r10,init_thread_union) // setup current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) tophys (r31,r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) l.sw TI_KSP(r31), r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) l.ori r4,r0,0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * .data contains initialized data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * .bss contains uninitialized data - clear it up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) clear_bss:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) LOAD_SYMBOL_2_GPR(r24, __bss_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) LOAD_SYMBOL_2_GPR(r26, _end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) tophys(r28,r24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) tophys(r30,r26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) CLEAR_GPR(r24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) CLEAR_GPR(r26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) l.sw (0)(r28),r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) l.sfltu r28,r30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) l.bf 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) l.addi r28,r28,4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) enable_ic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) l.jal _ic_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) enable_dc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) l.jal _dc_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) flush_tlb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) l.jal _flush_tlb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* The MMU needs to be enabled before or32_early_setup is called */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) enable_mmu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * enable dmmu & immu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * SR[5] = 0, SR[6] = 0, 6th and 7th bit of SR set to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) l.mfspr r30,r0,SPR_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) l.or r30,r30,r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) l.mtspr r0,r30,SPR_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) // reset the simulation counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) l.nop 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* check fdt header magic word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) l.lwz r3,0(r25) /* load magic from fdt into r3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) l.movhi r4,hi(OF_DT_HEADER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) l.ori r4,r4,lo(OF_DT_HEADER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) l.sfeq r3,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) l.bf _fdt_found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* magic number mismatch, set fdt pointer to null */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) l.or r25,r0,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) _fdt_found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* pass fdt pointer to or32_early_setup in r3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) l.or r3,r0,r25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) LOAD_SYMBOL_2_GPR(r24, or32_early_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) l.jalr r24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) clear_regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * clear all GPRS to increase determinism
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) CLEAR_GPR(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) CLEAR_GPR(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) CLEAR_GPR(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) CLEAR_GPR(r5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) CLEAR_GPR(r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) CLEAR_GPR(r7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) CLEAR_GPR(r8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) CLEAR_GPR(r9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) CLEAR_GPR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) CLEAR_GPR(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) CLEAR_GPR(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) CLEAR_GPR(r14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) CLEAR_GPR(r15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) CLEAR_GPR(r16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) CLEAR_GPR(r17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) CLEAR_GPR(r18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) CLEAR_GPR(r19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) CLEAR_GPR(r20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) CLEAR_GPR(r21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) CLEAR_GPR(r22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) CLEAR_GPR(r23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) CLEAR_GPR(r24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) CLEAR_GPR(r25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) CLEAR_GPR(r26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) CLEAR_GPR(r27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) CLEAR_GPR(r28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) CLEAR_GPR(r29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) CLEAR_GPR(r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) CLEAR_GPR(r31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) jump_start_kernel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * jump to kernel entry (start_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) LOAD_SYMBOL_2_GPR(r30, start_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) l.jr r30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) _flush_tlb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * I N V A L I D A T E T L B e n t r i e s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) l.addi r7,r0,128 /* Maximum number of sets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) l.mtspr r5,r0,0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) l.mtspr r6,r0,0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) l.addi r5,r5,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) l.addi r6,r6,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) l.sfeq r7,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) l.bnf 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) l.addi r7,r7,-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) l.jr r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) secondary_wait:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* Doze the cpu until we are asked to run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* If we dont have power management skip doze */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) l.mfspr r25,r0,SPR_UPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) l.andi r25,r25,SPR_UPR_PMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) l.sfeq r25,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) l.bf secondary_check_release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* Setup special secondary exception handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) LOAD_SYMBOL_2_GPR(r3, _secondary_evbar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) tophys(r25,r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) l.mtspr r0,r25,SPR_EVBAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* Enable Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) l.mfspr r25,r0,SPR_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) l.ori r25,r25,SPR_SR_IEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) l.mtspr r0,r25,SPR_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* Unmask interrupts interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) l.mfspr r25,r0,SPR_PICMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) l.ori r25,r25,0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) l.mtspr r0,r25,SPR_PICMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* Doze */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) l.mfspr r25,r0,SPR_PMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) LOAD_SYMBOL_2_GPR(r3, SPR_PMR_DME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) l.or r25,r25,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) l.mtspr r0,r25,SPR_PMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Wakeup - Restore exception handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) l.mtspr r0,r0,SPR_EVBAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) secondary_check_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * Check if we actually got the release signal, if not go-back to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) l.mfspr r25,r0,SPR_COREID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) LOAD_SYMBOL_2_GPR(r3, secondary_release)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) tophys(r4, r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) l.lwz r3,0(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) l.sfeq r25,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) l.bnf secondary_wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* fall through to secondary_init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) secondary_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * set up initial ksp and current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) LOAD_SYMBOL_2_GPR(r10, secondary_thread_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) tophys (r30,r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) l.lwz r10,0(r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) l.addi r1,r10,THREAD_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) tophys (r30,r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) l.sw TI_KSP(r30),r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) l.jal _ic_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) l.jal _dc_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) l.jal _flush_tlb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * enable dmmu & immu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) l.mfspr r30,r0,SPR_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) l.or r30,r30,r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * This is a bit tricky, we need to switch over from physical addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * to virtual addresses on the fly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * To do that, we first set up ESR with the IME and DME bits set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * Then EPCR is set to secondary_start and then a l.rfe is issued to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * "jump" to that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) l.mtspr r0,r30,SPR_ESR_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) LOAD_SYMBOL_2_GPR(r30, secondary_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) l.mtspr r0,r30,SPR_EPCR_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) l.rfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) secondary_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) LOAD_SYMBOL_2_GPR(r30, secondary_start_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) l.jr r30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* ========================================[ cache ]=== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* alignment here so we don't change memory offsets with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * memory controller defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .align 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) _ic_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* Check if IC present and skip enabling otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) l.mfspr r24,r0,SPR_UPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) l.andi r26,r24,SPR_UPR_ICP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) l.sfeq r26,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) l.bf 9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* Disable IC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) l.mfspr r6,r0,SPR_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) l.addi r5,r0,-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) l.xori r5,r5,SPR_SR_ICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) l.and r5,r6,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) l.mtspr r0,r5,SPR_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* Establish cache block size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) If BS=0, 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) If BS=1, 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) r14 contain block size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) l.mfspr r24,r0,SPR_ICCFGR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) l.andi r26,r24,SPR_ICCFGR_CBS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) l.srli r28,r26,7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) l.ori r30,r0,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) l.sll r14,r30,r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* Establish number of cache sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) r16 contains number of cache sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) r28 contains log(# of cache sets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) l.andi r26,r24,SPR_ICCFGR_NCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) l.srli r28,r26,3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) l.ori r30,r0,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) l.sll r16,r30,r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* Invalidate IC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) l.addi r6,r0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) l.sll r5,r14,r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) // l.mul r5,r14,r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) // l.trap 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) // l.addi r5,r0,IC_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) l.mtspr r0,r6,SPR_ICBIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) l.sfne r6,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) l.bf 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) l.add r6,r6,r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) // l.addi r6,r6,IC_LINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* Enable IC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) l.mfspr r6,r0,SPR_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) l.ori r6,r6,SPR_SR_ICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) l.mtspr r0,r6,SPR_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) l.jr r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) _dc_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Check if DC present and skip enabling otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) l.mfspr r24,r0,SPR_UPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) l.andi r26,r24,SPR_UPR_DCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) l.sfeq r26,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) l.bf 9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* Disable DC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) l.mfspr r6,r0,SPR_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) l.addi r5,r0,-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) l.xori r5,r5,SPR_SR_DCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) l.and r5,r6,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) l.mtspr r0,r5,SPR_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* Establish cache block size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) If BS=0, 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) If BS=1, 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) r14 contain block size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) l.mfspr r24,r0,SPR_DCCFGR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) l.andi r26,r24,SPR_DCCFGR_CBS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) l.srli r28,r26,7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) l.ori r30,r0,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) l.sll r14,r30,r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* Establish number of cache sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) r16 contains number of cache sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) r28 contains log(# of cache sets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) l.andi r26,r24,SPR_DCCFGR_NCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) l.srli r28,r26,3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) l.ori r30,r0,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) l.sll r16,r30,r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* Invalidate DC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) l.addi r6,r0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) l.sll r5,r14,r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) l.mtspr r0,r6,SPR_DCBIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) l.sfne r6,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) l.bf 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) l.add r6,r6,r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* Enable DC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) l.mfspr r6,r0,SPR_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) l.ori r6,r6,SPR_SR_DCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) l.mtspr r0,r6,SPR_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) l.jr r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* ===============================================[ page table masks ]=== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define DTLB_UP_CONVERT_MASK 0x3fa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define ITLB_UP_CONVERT_MASK 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* for SMP we'd have (this is a bit subtle, CC must be always set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * for SMP, but since we have _PAGE_PRESENT bit always defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * we can just modify the mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define DTLB_SMP_CONVERT_MASK 0x3fb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define ITLB_SMP_CONVERT_MASK 0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* ---[ boot dtlb miss handler ]----------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) boot_dtlb_miss_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* mask for DTLB_MR register: - (0) sets V (valid) bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * - (31-12) sets bits belonging to VPN (31-12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define DTLB_MR_MASK 0xfffff001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* mask for DTLB_TR register: - (2) sets CI (cache inhibit) bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * - (4) sets A (access) bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * - (5) sets D (dirty) bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * - (8) sets SRE (superuser read) bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * - (9) sets SWE (superuser write) bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * - (31-12) sets bits belonging to VPN (31-12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define DTLB_TR_MASK 0xfffff332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* These are for masking out the VPN/PPN value from the MR/TR registers...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * it's not the same as the PFN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define VPN_MASK 0xfffff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define PPN_MASK 0xfffff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) EXCEPTION_STORE_GPR6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) l.mfspr r6,r0,SPR_ESR_BASE //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) l.sfeqi r6,0 // r6 == 0x1 --> SM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) l.bf exit_with_no_dtranslation //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* this could be optimized by moving storing of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * non r6 registers here, and jumping r6 restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * if not in supervisor mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) EXCEPTION_STORE_GPR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) EXCEPTION_STORE_GPR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) EXCEPTION_STORE_GPR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) EXCEPTION_STORE_GPR5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) immediate_translation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) CLEAR_GPR(r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) l.mfspr r6, r0, SPR_DMMUCFGR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) l.andi r6, r6, SPR_DMMUCFGR_NTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) l.ori r5, r0, 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) l.sll r5, r5, r6 // r5 = number DMMU sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) l.addi r6, r5, -1 // r6 = nsets mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) l.or r6,r6,r4 // r6 <- r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) l.movhi r5,hi(DTLB_MR_MASK) // r5 <- ffff:0000.x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have DTLBMR entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* set up DTLB with no translation for EA <= 0xbfffffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) LOAD_SYMBOL_2_GPR(r6,0xbfffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) l.bf 1f // goto out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) tophys(r3,r4) // r3 <- PA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) l.movhi r5,hi(DTLB_TR_MASK) // r5 <- ffff:0000.x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) EXCEPTION_LOAD_GPR6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) EXCEPTION_LOAD_GPR5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) EXCEPTION_LOAD_GPR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) EXCEPTION_LOAD_GPR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) EXCEPTION_LOAD_GPR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) l.rfe // SR <- ESR, PC <- EPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) exit_with_no_dtranslation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* EA out of memory or not in supervisor mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) EXCEPTION_LOAD_GPR6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) EXCEPTION_LOAD_GPR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) l.j _dispatch_bus_fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* ---[ boot itlb miss handler ]----------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) boot_itlb_miss_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* mask for ITLB_MR register: - sets V (valid) bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * - sets bits belonging to VPN (15-12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define ITLB_MR_MASK 0xfffff001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /* mask for ITLB_TR register: - sets A (access) bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * - sets SXE (superuser execute) bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * - sets bits belonging to VPN (15-12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define ITLB_TR_MASK 0xfffff050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define VPN_MASK 0xffffe000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define PPN_MASK 0xffffe000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) EXCEPTION_STORE_GPR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) EXCEPTION_STORE_GPR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) EXCEPTION_STORE_GPR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) EXCEPTION_STORE_GPR5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) EXCEPTION_STORE_GPR6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) l.mfspr r6,r0,SPR_ESR_BASE //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) l.sfeqi r6,0 // r6 == 0x1 --> SM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) l.bf exit_with_no_itranslation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) earlyearly:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) CLEAR_GPR(r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) l.mfspr r6, r0, SPR_IMMUCFGR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) l.andi r6, r6, SPR_IMMUCFGR_NTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) l.ori r5, r0, 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) l.sll r5, r5, r6 // r5 = number IMMU sets from IMMUCFGR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) l.addi r6, r5, -1 // r6 = nsets mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) l.or r6,r6,r4 // r6 <- r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) l.movhi r5,hi(ITLB_MR_MASK) // r5 <- ffff:0000.x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have ITLBMR entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) l.mtspr r2,r5,SPR_ITLBMR_BASE(0) // set ITLBMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * set up ITLB with no translation for EA <= 0x0fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * we need this for head.S mapping (EA = PA). if we move all functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * which run with mmu enabled into entry.S, we might be able to eliminate this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) LOAD_SYMBOL_2_GPR(r6,0x0fffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) l.bf 1f // goto out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) tophys(r3,r4) // r3 <- PA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) l.movhi r5,hi(ITLB_TR_MASK) // r5 <- ffff:0000.x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) EXCEPTION_LOAD_GPR6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) EXCEPTION_LOAD_GPR5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) EXCEPTION_LOAD_GPR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) EXCEPTION_LOAD_GPR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) EXCEPTION_LOAD_GPR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) l.rfe // SR <- ESR, PC <- EPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) exit_with_no_itranslation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) EXCEPTION_LOAD_GPR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) EXCEPTION_LOAD_GPR6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) l.j _dispatch_bus_fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* ====================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * Stuff below here shouldn't go into .head section... maybe this stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * can be moved to entry.S ???
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* ==============================================[ DTLB miss handler ]=== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * Comments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * Exception handlers are entered with MMU off so the following handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * needs to use physical addressing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) ENTRY(dtlb_miss_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) EXCEPTION_STORE_GPR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) EXCEPTION_STORE_GPR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) EXCEPTION_STORE_GPR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * get EA of the miss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) l.mfspr r2,r0,SPR_EEAR_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) GET_CURRENT_PGD(r3,r4) // r3 is current_pgd, r4 is temp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) l.slli r4,r4,0x2 // to get address << 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) l.add r3,r4,r3 // r4 is pgd_index(daddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * if (pmd_none(*pmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * goto pmd_none:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) tophys (r4,r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) l.lwz r3,0x0(r4) // get *pmd value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) l.sfne r3,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) l.bnf d_pmd_none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) l.addi r3,r0,0xffffe000 // PAGE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) d_pmd_good:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * pte = *pte_offset(pmd, daddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) l.lwz r4,0x0(r4) // get **pmd value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) l.and r4,r4,r3 // & PAGE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) l.slli r3,r3,0x2 // to get address << 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) l.add r3,r3,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) l.lwz r3,0x0(r3) // this is pte at last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * if (!pte_present(pte))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) l.andi r4,r3,0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) l.sfne r4,r0 // is pte present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) l.bnf d_pte_not_present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) l.addi r4,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * fill DTLB TR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) l.and r4,r3,r4 // apply the mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) // Determine number of DMMU sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) l.mfspr r2, r0, SPR_DMMUCFGR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) l.andi r2, r2, SPR_DMMUCFGR_NTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) l.srli r2, r2, SPR_DMMUCFGR_NTS_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) l.ori r3, r0, 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) l.sll r3, r3, r2 // r3 = number DMMU sets DMMUCFGR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) l.addi r2, r3, -1 // r2 = nsets mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) l.mfspr r3, r0, SPR_EEAR_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) l.srli r3, r3, 0xd // >> PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) //NUM_TLB_ENTRIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) l.mtspr r2,r4,SPR_DTLBTR_BASE(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * fill DTLB MR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) l.mtspr r2,r4,SPR_DTLBMR_BASE(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) EXCEPTION_LOAD_GPR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) EXCEPTION_LOAD_GPR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) EXCEPTION_LOAD_GPR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) l.rfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) d_pmd_none:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) d_pte_not_present:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) EXCEPTION_LOAD_GPR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) EXCEPTION_LOAD_GPR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) EXCEPTION_LOAD_GPR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) EXCEPTION_HANDLE(_dtlb_miss_page_fault_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* ==============================================[ ITLB miss handler ]=== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ENTRY(itlb_miss_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) EXCEPTION_STORE_GPR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) EXCEPTION_STORE_GPR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) EXCEPTION_STORE_GPR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * get EA of the miss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) l.mfspr r2,r0,SPR_EEAR_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) GET_CURRENT_PGD(r3,r4) // r3 is current_pgd, r5 is temp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) l.slli r4,r4,0x2 // to get address << 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) l.add r3,r4,r3 // r4 is pgd_index(daddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * if (pmd_none(*pmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * goto pmd_none:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) tophys (r4,r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) l.lwz r3,0x0(r4) // get *pmd value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) l.sfne r3,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) l.bnf i_pmd_none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) l.addi r3,r0,0xffffe000 // PAGE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) i_pmd_good:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * pte = *pte_offset(pmd, iaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) l.lwz r4,0x0(r4) // get **pmd value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) l.and r4,r4,r3 // & PAGE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) l.slli r3,r3,0x2 // to get address << 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) l.add r3,r3,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) l.lwz r3,0x0(r3) // this is pte at last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * if (!pte_present(pte))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) l.andi r4,r3,0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) l.sfne r4,r0 // is pte present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) l.bnf i_pte_not_present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) l.addi r4,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * fill ITLB TR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) l.and r4,r3,r4 // apply the mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) l.andi r3,r3,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) l.sfeq r3,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) l.bf itlb_tr_fill //_workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) // Determine number of IMMU sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) l.mfspr r2, r0, SPR_IMMUCFGR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) l.andi r2, r2, SPR_IMMUCFGR_NTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) l.srli r2, r2, SPR_IMMUCFGR_NTS_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) l.ori r3, r0, 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) l.sll r3, r3, r2 // r3 = number IMMU sets IMMUCFGR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) l.addi r2, r3, -1 // r2 = nsets mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) l.mfspr r3, r0, SPR_EEAR_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) l.srli r3, r3, 0xd // >> PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * __PHX__ :: fixme
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * we should not just blindly set executable flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * but it does help with ping. the clean way would be to find out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * (and fix it) why stack doesn't have execution permissions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) itlb_tr_fill_workaround:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) itlb_tr_fill:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) l.mtspr r2,r4,SPR_ITLBTR_BASE(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * fill DTLB MR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) l.mtspr r2,r4,SPR_ITLBMR_BASE(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) EXCEPTION_LOAD_GPR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) EXCEPTION_LOAD_GPR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) EXCEPTION_LOAD_GPR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) l.rfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) i_pmd_none:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) i_pte_not_present:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) EXCEPTION_LOAD_GPR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) EXCEPTION_LOAD_GPR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) EXCEPTION_LOAD_GPR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) EXCEPTION_HANDLE(_itlb_miss_page_fault_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* ==============================================[ boot tlb handlers ]=== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /* =================================================[ debugging aids ]=== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .align 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) _immu_trampoline:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .space 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) _immu_trampoline_top:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define TRAMP_SLOT_0 (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define TRAMP_SLOT_1 (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define TRAMP_SLOT_2 (0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define TRAMP_SLOT_3 (0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define TRAMP_SLOT_4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define TRAMP_SLOT_5 (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define TRAMP_FRAME_SIZE (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) ENTRY(_immu_trampoline_workaround)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) // r2 EEA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) // r6 is physical EEA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) tophys(r6,r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) LOAD_SYMBOL_2_GPR(r5,_immu_trampoline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) tophys (r3,r5) // r3 is trampoline (physical)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) LOAD_SYMBOL_2_GPR(r4,0x15000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) l.sw TRAMP_SLOT_0(r3),r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) l.sw TRAMP_SLOT_1(r3),r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) l.sw TRAMP_SLOT_4(r3),r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) l.sw TRAMP_SLOT_5(r3),r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) // EPC = EEA - 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) l.lwz r4,0x0(r6) // load op @ EEA + 0x0 (fc address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) l.sw TRAMP_SLOT_3(r3),r4 // store it to _immu_trampoline_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) l.sw TRAMP_SLOT_2(r3),r4 // store it to _immu_trampoline_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) l.srli r5,r4,26 // check opcode for write access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) l.sfeqi r5,0 // l.j
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) l.bf 0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) l.sfeqi r5,0x11 // l.jr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) l.bf 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) l.sfeqi r5,1 // l.jal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) l.bf 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) l.sfeqi r5,0x12 // l.jalr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) l.bf 3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) l.sfeqi r5,3 // l.bnf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) l.bf 4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) l.sfeqi r5,4 // l.bf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) l.bf 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) 99:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) l.j 99b // should never happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) l.nop 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) // r2 is EEA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) // r3 is trampoline address (physical)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) // r4 is instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) // r6 is physical(EEA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) // r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) 2: // l.jal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) /* 19 20 aa aa l.movhi r9,0xaaaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * a9 29 bb bb l.ori r9,0xbbbb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) * where 0xaaaabbbb is EEA + 0x4 shifted right 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) l.addi r6,r2,0x4 // this is 0xaaaabbbb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) // l.movhi r9,0xaaaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) l.sh (TRAMP_SLOT_0+0x0)(r3),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) l.srli r5,r6,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) l.sh (TRAMP_SLOT_0+0x2)(r3),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) // l.ori r9,0xbbbb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) l.sh (TRAMP_SLOT_1+0x0)(r3),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) l.andi r5,r6,0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) l.sh (TRAMP_SLOT_1+0x2)(r3),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) /* falthrough, need to set up new jump offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) 0: // l.j
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) l.slli r6,r4,6 // original offset shifted left 6 - 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) // l.srli r6,r6,6 // original offset shifted right 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) l.slli r4,r2,4 // old jump position: EEA shifted left 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) // l.srli r4,r4,6 // old jump position: shifted right 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) l.addi r5,r3,0xc // new jump position (physical)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) l.slli r5,r5,4 // new jump position: shifted left 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) // calculate new jump offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) // new_off = old_off + (old_jump - new_jump)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) l.sub r5,r4,r5 // old_jump - new_jump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) l.add r5,r6,r5 // orig_off + (old_jump - new_jump)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) l.srli r5,r5,6 // new offset shifted right 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) // r5 is new jump offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) // l.j has opcode 0x0...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) l.sw TRAMP_SLOT_2(r3),r5 // write it back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) l.j trampoline_out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) /* ----------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) 3: // l.jalr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* 19 20 aa aa l.movhi r9,0xaaaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * a9 29 bb bb l.ori r9,0xbbbb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) * where 0xaaaabbbb is EEA + 0x4 shifted right 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) l.addi r6,r2,0x4 // this is 0xaaaabbbb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) // l.movhi r9,0xaaaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) l.sh (TRAMP_SLOT_0+0x0)(r3),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) l.srli r5,r6,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) l.sh (TRAMP_SLOT_0+0x2)(r3),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) // l.ori r9,0xbbbb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) l.sh (TRAMP_SLOT_1+0x0)(r3),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) l.andi r5,r6,0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) l.sh (TRAMP_SLOT_1+0x2)(r3),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) l.lhz r5,(TRAMP_SLOT_2+0x0)(r3) // load hi part of jump instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) l.andi r5,r5,0x3ff // clear out opcode part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) l.sh (TRAMP_SLOT_2+0x0)(r3),r5 // write it back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /* falthrough */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) 1: // l.jr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) l.j trampoline_out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /* ----------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) 4: // l.bnf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) 5: // l.bf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) l.slli r6,r4,6 // original offset shifted left 6 - 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) // l.srli r6,r6,6 // original offset shifted right 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) l.slli r4,r2,4 // old jump position: EEA shifted left 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) // l.srli r4,r4,6 // old jump position: shifted right 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) l.addi r5,r3,0xc // new jump position (physical)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) l.slli r5,r5,4 // new jump position: shifted left 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) // calculate new jump offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) // new_off = old_off + (old_jump - new_jump)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) l.add r6,r6,r4 // (orig_off + old_jump)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) l.sub r6,r6,r5 // (orig_off + old_jump) - new_jump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) l.srli r6,r6,6 // new offset shifted right 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) // r6 is new jump offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) l.lwz r4,(TRAMP_SLOT_2+0x0)(r3) // load jump instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) l.srli r4,r4,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) l.andi r4,r4,0xfc00 // get opcode part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) l.slli r4,r4,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) l.or r6,r4,r6 // l.b(n)f new offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) l.sw TRAMP_SLOT_2(r3),r6 // write it back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /* we need to add l.j to EEA + 0x8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) tophys (r4,r2) // may not be needed (due to shifts down_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) l.addi r4,r4,(0x8 - 0x8) // jump target = r2 + 0x8 (compensate for 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) // jump position = r5 + 0x8 (0x8 compensated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) l.sub r4,r4,r5 // jump offset = target - new_position + 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) l.slli r4,r4,4 // the amount of info in imediate of jump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) l.srli r4,r4,6 // jump instruction with offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) l.sw TRAMP_SLOT_4(r3),r4 // write it to 4th slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* fallthrough */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) trampoline_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) // set up new EPC to point to our trampoline code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) LOAD_SYMBOL_2_GPR(r5,_immu_trampoline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) l.mtspr r0,r5,SPR_EPCR_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) // immu_trampoline is (4x) CACHE_LINE aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) // and only 6 instructions long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) // so we need to invalidate only 2 lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /* Establish cache block size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) If BS=0, 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) If BS=1, 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) r14 contain block size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) l.mfspr r21,r0,SPR_ICCFGR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) l.andi r21,r21,SPR_ICCFGR_CBS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) l.srli r21,r21,7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) l.ori r23,r0,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) l.sll r14,r23,r21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) l.mtspr r0,r5,SPR_ICBIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) l.add r5,r5,r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) l.mtspr r0,r5,SPR_ICBIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) l.jr r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) * DSCR: prints a string referenced by r3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) * PRMS: r3 - address of the first character of null
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) * terminated string to be printed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * PREQ: UART at UART_BASE_ADD has to be initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) * POST: caller should be aware that r3, r9 are changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) ENTRY(_emergency_print)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) EMERGENCY_PRINT_STORE_GPR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) EMERGENCY_PRINT_STORE_GPR5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) EMERGENCY_PRINT_STORE_GPR6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) EMERGENCY_PRINT_STORE_GPR7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) l.lbz r7,0(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) l.sfeq r7,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) l.bf 9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) // putc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) l.movhi r4,hi(UART_BASE_ADD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) l.addi r6,r0,0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) 1: l.lbz r5,5(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) l.andi r5,r5,0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) l.sfeq r5,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) l.bnf 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) l.sb 0(r4),r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) l.addi r6,r0,0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) 1: l.lbz r5,5(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) l.andi r5,r5,0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) l.sfeq r5,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) l.bnf 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /* next character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) l.j 2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) l.addi r3,r3,0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) EMERGENCY_PRINT_LOAD_GPR7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) EMERGENCY_PRINT_LOAD_GPR6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) EMERGENCY_PRINT_LOAD_GPR5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) EMERGENCY_PRINT_LOAD_GPR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) l.jr r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) ENTRY(_emergency_print_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) EMERGENCY_PRINT_STORE_GPR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) EMERGENCY_PRINT_STORE_GPR5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) EMERGENCY_PRINT_STORE_GPR6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) EMERGENCY_PRINT_STORE_GPR7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) EMERGENCY_PRINT_STORE_GPR8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) l.addi r8,r0,32 // shift register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) 1: /* remove leading zeros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) l.addi r8,r8,-0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) l.srl r7,r3,r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) l.andi r7,r7,0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /* don't skip the last zero if number == 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) l.sfeqi r8,0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) l.bf 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) l.sfeq r7,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) l.bf 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) l.srl r7,r3,r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) l.andi r7,r7,0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) l.sflts r8,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) l.bf 9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) l.sfgtui r7,0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) l.bnf 8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) l.addi r7,r7,0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) l.addi r7,r7,0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) // putc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) l.movhi r4,hi(UART_BASE_ADD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) l.addi r6,r0,0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) 1: l.lbz r5,5(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) l.andi r5,r5,0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) l.sfeq r5,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) l.bnf 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) l.sb 0(r4),r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) l.addi r6,r0,0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) 1: l.lbz r5,5(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) l.andi r5,r5,0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) l.sfeq r5,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) l.bnf 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /* next character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) l.j 2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) l.addi r8,r8,-0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) EMERGENCY_PRINT_LOAD_GPR8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) EMERGENCY_PRINT_LOAD_GPR7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) EMERGENCY_PRINT_LOAD_GPR6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) EMERGENCY_PRINT_LOAD_GPR5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) EMERGENCY_PRINT_LOAD_GPR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) l.jr r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) * This should be used for debugging only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) * It messes up the Linux early serial output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) * somehow, so use it sparingly and essentially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) * only if you need to debug something that goes wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) * before Linux gets the early serial going.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) * Furthermore, you'll have to make sure you set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) * UART_DEVISOR correctly according to the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) * clock rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) #define SYS_CLK 20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) //#define SYS_CLK 1843200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) #define OR32_CONSOLE_BAUD 115200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) #define UART_DIVISOR SYS_CLK/(16*OR32_CONSOLE_BAUD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) ENTRY(_early_uart_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) l.movhi r3,hi(UART_BASE_ADD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) l.addi r4,r0,0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) l.sb 0x2(r3),r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) l.addi r4,r0,0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) l.sb 0x1(r3),r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) l.addi r4,r0,0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) l.sb 0x3(r3),r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) l.lbz r5,3(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) l.ori r4,r5,0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) l.sb 0x3(r3),r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) l.sb UART_DLM(r3),r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) l.sb UART_DLL(r3),r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) l.sb 0x3(r3),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) l.jr r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .align 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .global _secondary_evbar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) _secondary_evbar:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .space 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) /* Just disable interrupts and Return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) l.ori r3,r0,SPR_SR_SM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) l.mtspr r0,r3,SPR_ESR_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) l.rfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .section .rodata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) _string_unhandled_exception:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .string "\n\rRunarunaround: Unhandled exception 0x\0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) _string_epc_prefix:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .string ": EPC=0x\0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) _string_nl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .string "\n\r\0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) /* ========================================[ page aligned structures ]=== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) * .data section should be page aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) * (look into arch/openrisc/kernel/vmlinux.lds.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .section .data,"aw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .align 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .global empty_zero_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) empty_zero_page:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .space 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .global swapper_pg_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) swapper_pg_dir:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .space 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .global _unhandled_stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) _unhandled_stack:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .space 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) _unhandled_stack_top:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) /* ============================================================[ EOF ]=== */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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