^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OpenRISC entry.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Linux architectural port borrowing liberally from similar works of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * others. All original copyrights apply as per the original source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * declaration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Modifications for the OpenRISC architecture:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2005 Gyorgy Jeney <nog@bsemi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/spr_defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DISABLE_INTERRUPTS(t1,t2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) l.mfspr t2,r0,SPR_SR ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) l.movhi t1,hi(~(SPR_SR_IEE|SPR_SR_TEE)) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) l.ori t1,t1,lo(~(SPR_SR_IEE|SPR_SR_TEE)) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) l.and t2,t2,t1 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) l.mtspr r0,t2,SPR_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ENABLE_INTERRUPTS(t1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) l.mfspr t1,r0,SPR_SR ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) l.ori t1,t1,lo(SPR_SR_IEE|SPR_SR_TEE) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) l.mtspr r0,t1,SPR_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* =========================================================[ macros ]=== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #ifdef CONFIG_TRACE_IRQFLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Trace irq on/off creating a stack frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TRACE_IRQS_OP(trace_op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) l.sw -8(r1),r2 /* store frame pointer */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) l.sw -4(r1),r9 /* store return address */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) l.addi r2,r1,0 /* move sp to fp */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) l.jal trace_op ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) l.addi r1,r1,-8 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) l.ori r1,r2,0 /* restore sp */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) l.lwz r9,-4(r1) /* restore return address */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) l.lwz r2,-8(r1) /* restore fp */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Trace irq on/off and save registers we need that would otherwise be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * clobbered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TRACE_IRQS_SAVE(t1,trace_op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) l.sw -12(r1),t1 /* save extra reg */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) l.sw -8(r1),r2 /* store frame pointer */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) l.sw -4(r1),r9 /* store return address */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) l.addi r2,r1,0 /* move sp to fp */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) l.jal trace_op ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) l.addi r1,r1,-12 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) l.ori r1,r2,0 /* restore sp */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) l.lwz r9,-4(r1) /* restore return address */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) l.lwz r2,-8(r1) /* restore fp */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) l.lwz t1,-12(r1) /* restore extra reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TRACE_IRQS_OFF TRACE_IRQS_OP(trace_hardirqs_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TRACE_IRQS_ON TRACE_IRQS_OP(trace_hardirqs_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TRACE_IRQS_ON_SYSCALL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) TRACE_IRQS_SAVE(r10,trace_hardirqs_on) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) l.lwz r3,PT_GPR3(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) l.lwz r4,PT_GPR4(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) l.lwz r5,PT_GPR5(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) l.lwz r6,PT_GPR6(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) l.lwz r7,PT_GPR7(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) l.lwz r8,PT_GPR8(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) l.lwz r11,PT_GPR11(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TRACE_IRQS_OFF_ENTRY \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) l.lwz r5,PT_SR(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) l.andi r3,r5,(SPR_SR_IEE|SPR_SR_TEE) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) l.sfeq r5,r0 /* skip trace if irqs were already off */;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) l.bf 1f ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) l.nop ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) TRACE_IRQS_SAVE(r4,trace_hardirqs_off) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TRACE_IRQS_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TRACE_IRQS_ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TRACE_IRQS_OFF_ENTRY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TRACE_IRQS_ON_SYSCALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * We need to disable interrupts at beginning of RESTORE_ALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * since interrupt might come in after we've loaded EPC return address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * and overwrite EPC with address somewhere in RESTORE_ALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * which is of course wrong!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RESTORE_ALL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DISABLE_INTERRUPTS(r3,r4) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) l.lwz r3,PT_PC(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) l.mtspr r0,r3,SPR_EPCR_BASE ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) l.lwz r3,PT_SR(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) l.mtspr r0,r3,SPR_ESR_BASE ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) l.lwz r2,PT_GPR2(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) l.lwz r3,PT_GPR3(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) l.lwz r4,PT_GPR4(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) l.lwz r5,PT_GPR5(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) l.lwz r6,PT_GPR6(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) l.lwz r7,PT_GPR7(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) l.lwz r8,PT_GPR8(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) l.lwz r9,PT_GPR9(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) l.lwz r10,PT_GPR10(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) l.lwz r11,PT_GPR11(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) l.lwz r12,PT_GPR12(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) l.lwz r13,PT_GPR13(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) l.lwz r14,PT_GPR14(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) l.lwz r15,PT_GPR15(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) l.lwz r16,PT_GPR16(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) l.lwz r17,PT_GPR17(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) l.lwz r18,PT_GPR18(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) l.lwz r19,PT_GPR19(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) l.lwz r20,PT_GPR20(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) l.lwz r21,PT_GPR21(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) l.lwz r22,PT_GPR22(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) l.lwz r23,PT_GPR23(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) l.lwz r24,PT_GPR24(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) l.lwz r25,PT_GPR25(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) l.lwz r26,PT_GPR26(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) l.lwz r27,PT_GPR27(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) l.lwz r28,PT_GPR28(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) l.lwz r29,PT_GPR29(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) l.lwz r30,PT_GPR30(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) l.lwz r31,PT_GPR31(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) l.lwz r1,PT_SP(r1) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) l.rfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define EXCEPTION_ENTRY(handler) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .global handler ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) handler: ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* r1, EPCR, ESR a already saved */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) l.sw PT_GPR2(r1),r2 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) l.sw PT_GPR3(r1),r3 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* r4 already save */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) l.sw PT_GPR5(r1),r5 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) l.sw PT_GPR6(r1),r6 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) l.sw PT_GPR7(r1),r7 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) l.sw PT_GPR8(r1),r8 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) l.sw PT_GPR9(r1),r9 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* r10 already saved */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) l.sw PT_GPR11(r1),r11 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* r12 already saved */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) l.sw PT_GPR13(r1),r13 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) l.sw PT_GPR14(r1),r14 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) l.sw PT_GPR15(r1),r15 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) l.sw PT_GPR16(r1),r16 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) l.sw PT_GPR17(r1),r17 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) l.sw PT_GPR18(r1),r18 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) l.sw PT_GPR19(r1),r19 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) l.sw PT_GPR20(r1),r20 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) l.sw PT_GPR21(r1),r21 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) l.sw PT_GPR22(r1),r22 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) l.sw PT_GPR23(r1),r23 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) l.sw PT_GPR24(r1),r24 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) l.sw PT_GPR25(r1),r25 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) l.sw PT_GPR26(r1),r26 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) l.sw PT_GPR27(r1),r27 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) l.sw PT_GPR28(r1),r28 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) l.sw PT_GPR29(r1),r29 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* r30 already save */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* l.sw PT_GPR30(r1),r30*/ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) l.sw PT_GPR31(r1),r31 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) TRACE_IRQS_OFF_ENTRY ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) l.addi r30,r0,-1 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) l.sw PT_ORIG_GPR11(r1),r30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define UNHANDLED_EXCEPTION(handler,vector) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .global handler ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) handler: ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* r1, EPCR, ESR already saved */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) l.sw PT_GPR2(r1),r2 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) l.sw PT_GPR3(r1),r3 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) l.sw PT_GPR5(r1),r5 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) l.sw PT_GPR6(r1),r6 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) l.sw PT_GPR7(r1),r7 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) l.sw PT_GPR8(r1),r8 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) l.sw PT_GPR9(r1),r9 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* r10 already saved */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) l.sw PT_GPR11(r1),r11 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* r12 already saved */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) l.sw PT_GPR13(r1),r13 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) l.sw PT_GPR14(r1),r14 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) l.sw PT_GPR15(r1),r15 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) l.sw PT_GPR16(r1),r16 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) l.sw PT_GPR17(r1),r17 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) l.sw PT_GPR18(r1),r18 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) l.sw PT_GPR19(r1),r19 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) l.sw PT_GPR20(r1),r20 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) l.sw PT_GPR21(r1),r21 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) l.sw PT_GPR22(r1),r22 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) l.sw PT_GPR23(r1),r23 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) l.sw PT_GPR24(r1),r24 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) l.sw PT_GPR25(r1),r25 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) l.sw PT_GPR26(r1),r26 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) l.sw PT_GPR27(r1),r27 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) l.sw PT_GPR28(r1),r28 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) l.sw PT_GPR29(r1),r29 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* r31 already saved */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) l.sw PT_GPR30(r1),r30 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* l.sw PT_GPR31(r1),r31 */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) l.addi r30,r0,-1 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) l.sw PT_ORIG_GPR11(r1),r30 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) l.addi r3,r1,0 ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* r4 is exception EA */ ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) l.addi r5,r0,vector ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) l.jal unhandled_exception ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) l.nop ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) l.j _ret_from_exception ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* clobbers 'reg' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CLEAR_LWA_FLAG(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) l.movhi reg,hi(lwa_flag) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) l.ori reg,reg,lo(lwa_flag) ;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) l.sw 0(reg),r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * NOTE: one should never assume that SPR_EPC, SPR_ESR, SPR_EEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * contain the same values as when exception we're handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * occured. in fact they never do. if you need them use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * values saved on stack (for SPR_EPC, SPR_ESR) or content
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * of r4 (for SPR_EEAR). for details look at EXCEPTION_HANDLE()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * in 'arch/openrisc/kernel/head.S'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* =====================================================[ exceptions] === */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* ---[ 0x100: RESET exception ]----------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) EXCEPTION_ENTRY(_tng_kernel_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) l.jal _start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) l.andi r0,r0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* ---[ 0x200: BUS exception ]------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) EXCEPTION_ENTRY(_bus_fault_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) CLEAR_LWA_FLAG(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* r4: EA of fault (set by EXCEPTION_HANDLE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) l.jal do_bus_fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) l.addi r3,r1,0 /* pt_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) l.j _ret_from_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) EXCEPTION_ENTRY(_dtlb_miss_page_fault_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) CLEAR_LWA_FLAG(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) l.and r5,r5,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) l.j 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) EXCEPTION_ENTRY(_data_page_fault_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) CLEAR_LWA_FLAG(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* set up parameters for do_page_fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) l.ori r5,r0,0x300 // exception vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) l.addi r3,r1,0 // pt_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* r4 set be EXCEPTION_HANDLE */ // effective address of fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) l.lwz r6,PT_PC(r3) // address of an offending insn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) l.lwz r6,0(r6) // instruction that caused pf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) l.srli r6,r6,26 // check opcode for jump insn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) l.sfeqi r6,0 // l.j
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) l.bf 8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) l.sfeqi r6,1 // l.jal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) l.bf 8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) l.sfeqi r6,3 // l.bnf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) l.bf 8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) l.sfeqi r6,4 // l.bf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) l.bf 8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) l.sfeqi r6,0x11 // l.jr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) l.bf 8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) l.sfeqi r6,0x12 // l.jalr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) l.bf 8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) l.j 9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 8: // offending insn is in delay slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) l.lwz r6,PT_PC(r3) // address of an offending insn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) l.addi r6,r6,4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) l.lwz r6,0(r6) // instruction that caused pf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) l.srli r6,r6,26 // get opcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 9: // offending instruction opcode loaded in r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) l.mfspr r6,r0,SPR_SR // SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) l.andi r6,r6,SPR_SR_DSX // check for delay slot exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) l.sfne r6,r0 // exception happened in delay slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) l.bnf 7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) l.lwz r6,PT_PC(r3) // address of an offending insn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) l.addi r6,r6,4 // offending insn is in delay slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) l.lwz r6,0(r6) // instruction that caused pf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) l.srli r6,r6,26 // check opcode for write access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) l.sfgeui r6,0x33 // check opcode for write access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) l.bnf 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) l.sfleui r6,0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) l.bnf 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) l.ori r6,r0,0x1 // write access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) l.j 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 1: l.ori r6,r0,0x0 // !write access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* call fault.c handler in or32/mm/fault.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) l.jal do_page_fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) l.j _ret_from_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) CLEAR_LWA_FLAG(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) l.and r5,r5,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) l.j 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) EXCEPTION_ENTRY(_insn_page_fault_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) CLEAR_LWA_FLAG(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* set up parameters for do_page_fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) l.ori r5,r0,0x400 // exception vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) l.addi r3,r1,0 // pt_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* r4 set be EXCEPTION_HANDLE */ // effective address of fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) l.ori r6,r0,0x0 // !write access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* call fault.c handler in or32/mm/fault.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) l.jal do_page_fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) l.j _ret_from_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* ---[ 0x500: Timer exception ]----------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) EXCEPTION_ENTRY(_timer_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) CLEAR_LWA_FLAG(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) l.jal timer_interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) l.addi r3,r1,0 /* pt_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) l.j _ret_from_intr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* ---[ 0x600: Alignment exception ]-------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) EXCEPTION_ENTRY(_alignment_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) CLEAR_LWA_FLAG(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* r4: EA of fault (set by EXCEPTION_HANDLE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) l.jal do_unaligned_access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) l.addi r3,r1,0 /* pt_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) l.j _ret_from_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) EXCEPTION_ENTRY(_alignment_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) // l.mfspr r2,r0,SPR_EEAR_BASE /* Load the effective address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) l.addi r2,r4,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) // l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) l.lwz r5,PT_PC(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) l.lwz r3,0(r5) /* Load insn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) l.srli r4,r3,26 /* Shift left to get the insn opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) l.bf jmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) l.sfeqi r4,0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) l.bf jmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) l.sfeqi r4,0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) l.bf jmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) l.sfeqi r4,0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) l.bf jmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) l.sfeqi r4,0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) l.bf jr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) l.sfeqi r4,0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) l.bf jr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) l.j 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) l.addi r5,r5,4 /* Increment PC to get return insn address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) jmp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) l.slli r4,r3,6 /* Get the signed extended jump length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) l.srai r4,r4,4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) l.lwz r3,4(r5) /* Load the real load/store insn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) l.add r5,r5,r4 /* Calculate jump target address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) l.j 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) l.srli r4,r3,26 /* Shift left to get the insn opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) jr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) l.slli r4,r3,9 /* Shift to get the reg nb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) l.andi r4,r4,0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) l.lwz r3,4(r5) /* Load the real load/store insn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) l.add r4,r4,r1 /* Load the jump register value from the stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) l.lwz r5,0(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) l.srli r4,r3,26 /* Shift left to get the insn opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) // l.mtspr r0,r5,SPR_EPCR_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) l.sw PT_PC(r1),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) l.sfeqi r4,0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) l.bf lhs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) l.sfeqi r4,0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) l.bf lhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) l.sfeqi r4,0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) l.bf lws
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) l.sfeqi r4,0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) l.bf lwz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) l.sfeqi r4,0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) l.bf sh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) l.sfeqi r4,0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) l.bf sw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 1: l.j 1b /* I don't know what to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) lhs: l.lbs r5,0(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) l.slli r5,r5,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) l.lbz r6,1(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) l.or r5,r5,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) l.srli r4,r3,19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) l.andi r4,r4,0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) l.add r4,r4,r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) l.j align_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) l.sw 0(r4),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) lhz: l.lbz r5,0(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) l.slli r5,r5,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) l.lbz r6,1(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) l.or r5,r5,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) l.srli r4,r3,19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) l.andi r4,r4,0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) l.add r4,r4,r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) l.j align_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) l.sw 0(r4),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) lws: l.lbs r5,0(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) l.slli r5,r5,24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) l.lbz r6,1(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) l.slli r6,r6,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) l.or r5,r5,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) l.lbz r6,2(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) l.slli r6,r6,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) l.or r5,r5,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) l.lbz r6,3(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) l.or r5,r5,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) l.srli r4,r3,19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) l.andi r4,r4,0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) l.add r4,r4,r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) l.j align_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) l.sw 0(r4),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) lwz: l.lbz r5,0(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) l.slli r5,r5,24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) l.lbz r6,1(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) l.slli r6,r6,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) l.or r5,r5,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) l.lbz r6,2(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) l.slli r6,r6,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) l.or r5,r5,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) l.lbz r6,3(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) l.or r5,r5,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) l.srli r4,r3,19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) l.andi r4,r4,0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) l.add r4,r4,r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) l.j align_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) l.sw 0(r4),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) sh:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) l.srli r4,r3,9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) l.andi r4,r4,0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) l.add r4,r4,r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) l.lwz r5,0(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) l.sb 1(r2),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) l.srli r5,r5,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) l.j align_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) l.sb 0(r2),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) sw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) l.srli r4,r3,9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) l.andi r4,r4,0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) l.add r4,r4,r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) l.lwz r5,0(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) l.sb 3(r2),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) l.srli r5,r5,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) l.sb 2(r2),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) l.srli r5,r5,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) l.sb 1(r2),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) l.srli r5,r5,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) l.j align_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) l.sb 0(r2),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) align_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) l.j _ret_from_intr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) EXCEPTION_ENTRY(_illegal_instruction_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* r4: EA of fault (set by EXCEPTION_HANDLE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) l.jal do_illegal_instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) l.addi r3,r1,0 /* pt_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) l.j _ret_from_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* ---[ 0x800: External interrupt exception ]---------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) EXCEPTION_ENTRY(_external_irq_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #ifdef CONFIG_OPENRISC_ESR_EXCEPTION_BUG_CHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) l.lwz r4,PT_SR(r1) // were interrupts enabled ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) l.andi r4,r4,SPR_SR_IEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) l.sfeqi r4,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) l.bnf 1f // ext irq enabled, all ok.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #ifdef CONFIG_PRINTK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) l.addi r1,r1,-0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) l.movhi r3,hi(42f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) l.ori r3,r3,lo(42f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) l.sw 0x0(r1),r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) l.jal printk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) l.sw 0x4(r1),r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) l.addi r1,r1,0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .section .rodata, "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 42:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .string "\n\rESR interrupt bug: in _external_irq_handler (ESR %x)\n\r"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .align 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) l.ori r4,r4,SPR_SR_IEE // fix the bug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) // l.sw PT_SR(r1),r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) CLEAR_LWA_FLAG(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) l.addi r3,r1,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) l.movhi r8,hi(do_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) l.ori r8,r8,lo(do_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) l.jalr r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) l.j _ret_from_intr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* ---[ 0xb00: Range exception ]----------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) UNHANDLED_EXCEPTION(_vector_0xb00,0xb00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * Syscalls are a special type of exception in that they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * _explicitly_ invoked by userspace and can therefore be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * held to conform to the same ABI as normal functions with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * respect to whether registers are preserved across the call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Upon syscall entry we just save the callee-saved registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * and not the call-clobbered ones.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) _string_syscall_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .string "syscall return %ld \n\r\0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .align 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ENTRY(_sys_call_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* r1, EPCR, ESR a already saved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) l.sw PT_GPR2(r1),r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* r3-r8 must be saved because syscall restart relies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * on us being able to restart the syscall args... technically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * they should be clobbered, otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) l.sw PT_GPR3(r1),r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * r4 already saved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * r4 holds the EEAR address of the fault, use it as screatch reg and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * then load the original r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) CLEAR_LWA_FLAG(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) l.lwz r4,PT_GPR4(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) l.sw PT_GPR5(r1),r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) l.sw PT_GPR6(r1),r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) l.sw PT_GPR7(r1),r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) l.sw PT_GPR8(r1),r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) l.sw PT_GPR9(r1),r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* r10 already saved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) l.sw PT_GPR11(r1),r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* orig_gpr11 must be set for syscalls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) l.sw PT_ORIG_GPR11(r1),r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* r12,r13 already saved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* r14-r28 (even) aren't touched by the syscall fast path below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * so we don't need to save them. However, the functions that return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * to userspace via a call to switch() DO need to save these because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * switch() effectively clobbers them... saving these registers for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * such functions is handled in their syscall wrappers (see fork, vfork,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * and clone, below).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* r30 is the only register we clobber in the fast path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* r30 already saved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* l.sw PT_GPR30(r1),r30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) _syscall_check_trace_enter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* syscalls run with interrupts enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) TRACE_IRQS_ON_SYSCALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ENABLE_INTERRUPTS(r29) // enable interrupts, r29 is temp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* If TIF_SYSCALL_TRACE is set, then we want to do syscall tracing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) l.lwz r30,TI_FLAGS(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) l.andi r30,r30,_TIF_SYSCALL_TRACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) l.sfne r30,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) l.bf _syscall_trace_enter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) _syscall_check:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* Ensure that the syscall number is reasonable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) l.sfgeui r11,__NR_syscalls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) l.bf _syscall_badsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) _syscall_call:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) l.movhi r29,hi(sys_call_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) l.ori r29,r29,lo(sys_call_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) l.slli r11,r11,2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) l.add r29,r29,r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) l.lwz r29,0(r29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) l.jalr r29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) _syscall_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* All syscalls return here... just pay attention to ret_from_fork
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * which does it in a round-about way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) l.sw PT_GPR11(r1),r11 // save return value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) _syscall_debug:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) l.movhi r3,hi(_string_syscall_return)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) l.ori r3,r3,lo(_string_syscall_return)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) l.ori r27,r0,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) l.sw -4(r1),r27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) l.sw -8(r1),r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) l.addi r1,r1,-8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) l.movhi r27,hi(printk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) l.ori r27,r27,lo(printk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) l.jalr r27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) l.addi r1,r1,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) _syscall_check_trace_leave:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* r30 is a callee-saved register so this should still hold the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * _TIF_SYSCALL_TRACE flag from _syscall_check_trace_enter above...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * _syscall_trace_leave expects syscall result to be in pt_regs->r11.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) l.sfne r30,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) l.bf _syscall_trace_leave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* This is where the exception-return code begins... interrupts need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * disabled the rest of the way here because we can't afford to miss any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * interrupts that set NEED_RESCHED or SIGNALPENDING... really true? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) _syscall_check_work:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* Here we need to disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) DISABLE_INTERRUPTS(r27,r29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) TRACE_IRQS_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) l.lwz r30,TI_FLAGS(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) l.andi r30,r30,_TIF_WORK_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) l.sfne r30,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) l.bnf _syscall_resume_userspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* Work pending follows a different return path, so we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * make sure that all the call-saved registers get into pt_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * before branching...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) l.sw PT_GPR14(r1),r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) l.sw PT_GPR16(r1),r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) l.sw PT_GPR18(r1),r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) l.sw PT_GPR20(r1),r20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) l.sw PT_GPR22(r1),r22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) l.sw PT_GPR24(r1),r24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) l.sw PT_GPR26(r1),r26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) l.sw PT_GPR28(r1),r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* _work_pending needs to be called with interrupts disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) l.j _work_pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) _syscall_resume_userspace:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) // ENABLE_INTERRUPTS(r29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* This is the hot path for returning to userspace from a syscall. If there's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * work to be done and the branch to _work_pending was taken above, then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * return to userspace will be done via the normal exception return path...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * that path restores _all_ registers and will overwrite the "clobbered"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * registers with whatever garbage is in pt_regs -- that's OK because those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * registers are clobbered anyway and because the extra work is insignificant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * in the context of the extra work that _work_pending is doing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* Once again, syscalls are special and only guarantee to preserve the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * same registers as a normal function call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* The assumption here is that the registers r14-r28 (even) are untouched and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * don't need to be restored... be sure that that's really the case!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* This is still too much... we should only be restoring what we actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * clobbered... we should even be using 'scratch' (odd) regs above so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * we don't need to restore anything, hardly...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) l.lwz r2,PT_GPR2(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* Restore args */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* r3-r8 are technically clobbered, but syscall restart needs these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * to be restored...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) l.lwz r3,PT_GPR3(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) l.lwz r4,PT_GPR4(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) l.lwz r5,PT_GPR5(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) l.lwz r6,PT_GPR6(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) l.lwz r7,PT_GPR7(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) l.lwz r8,PT_GPR8(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) l.lwz r9,PT_GPR9(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) l.lwz r10,PT_GPR10(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) l.lwz r11,PT_GPR11(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* r30 is the only register we clobber in the fast path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) l.lwz r30,PT_GPR30(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* Here we use r13-r19 (odd) as scratch regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) l.lwz r13,PT_PC(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) l.lwz r15,PT_SR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) l.lwz r1,PT_SP(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Interrupts need to be disabled for setting EPCR and ESR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * so that another interrupt doesn't come in here and clobber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * them before we can use them for our l.rfe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) DISABLE_INTERRUPTS(r17,r19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) l.mtspr r0,r13,SPR_EPCR_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) l.mtspr r0,r15,SPR_ESR_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) l.rfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* End of hot path!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * Keep the below tracing and error handling out of the hot path...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) _syscall_trace_enter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* Here we pass pt_regs to do_syscall_trace_enter. Make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * that function is really getting all the info it needs as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * pt_regs isn't a complete set of userspace regs, just the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * ones relevant to the syscall...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * Note use of delay slot for setting argument.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) l.jal do_syscall_trace_enter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) l.addi r3,r1,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* Restore arguments (not preserved across do_syscall_trace_enter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * so that we can do the syscall for real and return to the syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * hot path.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) l.lwz r11,PT_GPR11(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) l.lwz r3,PT_GPR3(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) l.lwz r4,PT_GPR4(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) l.lwz r5,PT_GPR5(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) l.lwz r6,PT_GPR6(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) l.lwz r7,PT_GPR7(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) l.j _syscall_check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) l.lwz r8,PT_GPR8(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) _syscall_trace_leave:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) l.jal do_syscall_trace_leave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) l.addi r3,r1,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) l.j _syscall_check_work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) _syscall_badsys:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* Here we effectively pretend to have executed an imaginary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * syscall that returns -ENOSYS and then return to the regular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * syscall hot path.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * Note that "return value" is set in the delay slot...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) l.j _syscall_return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) l.addi r11,r0,-ENOSYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /******* END SYSCALL HANDLING *******/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* ---[ 0xd00: Trap exception ]------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) UNHANDLED_EXCEPTION(_vector_0xd00,0xd00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* ---[ 0xe00: Trap exception ]------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) EXCEPTION_ENTRY(_trap_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) CLEAR_LWA_FLAG(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* r4: EA of fault (set by EXCEPTION_HANDLE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) l.jal do_trap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) l.addi r3,r1,0 /* pt_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) l.j _ret_from_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) UNHANDLED_EXCEPTION(_vector_0xf00,0xf00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* ---[ 0x1000: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) UNHANDLED_EXCEPTION(_vector_0x1000,0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* ---[ 0x1100: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) UNHANDLED_EXCEPTION(_vector_0x1100,0x1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* ---[ 0x1200: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) UNHANDLED_EXCEPTION(_vector_0x1200,0x1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* ---[ 0x1300: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) UNHANDLED_EXCEPTION(_vector_0x1300,0x1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* ---[ 0x1400: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) UNHANDLED_EXCEPTION(_vector_0x1400,0x1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* ---[ 0x1500: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) UNHANDLED_EXCEPTION(_vector_0x1500,0x1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* ---[ 0x1600: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) UNHANDLED_EXCEPTION(_vector_0x1600,0x1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* ---[ 0x1700: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) UNHANDLED_EXCEPTION(_vector_0x1700,0x1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* ---[ 0x1800: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) UNHANDLED_EXCEPTION(_vector_0x1800,0x1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* ---[ 0x1900: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) UNHANDLED_EXCEPTION(_vector_0x1900,0x1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) UNHANDLED_EXCEPTION(_vector_0x1a00,0x1a00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) UNHANDLED_EXCEPTION(_vector_0x1b00,0x1b00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) UNHANDLED_EXCEPTION(_vector_0x1c00,0x1c00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) UNHANDLED_EXCEPTION(_vector_0x1d00,0x1d00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) UNHANDLED_EXCEPTION(_vector_0x1e00,0x1e00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* ========================================================[ return ] === */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) _resume_userspace:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) DISABLE_INTERRUPTS(r3,r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) TRACE_IRQS_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) l.lwz r4,TI_FLAGS(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) l.andi r13,r4,_TIF_WORK_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) l.sfeqi r13,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) l.bf _restore_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) _work_pending:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) l.lwz r5,PT_ORIG_GPR11(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) l.sfltsi r5,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) l.bnf 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) l.andi r5,r5,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) l.jal do_work_pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) l.ori r3,r1,0 /* pt_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) l.sfeqi r11,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) l.bf _restore_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) l.sfltsi r11,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) l.bnf 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) l.and r11,r11,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) l.ori r11,r11,__NR_restart_syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) l.j _syscall_check_trace_enter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) l.lwz r11,PT_ORIG_GPR11(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* Restore arg registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) l.lwz r3,PT_GPR3(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) l.lwz r4,PT_GPR4(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) l.lwz r5,PT_GPR5(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) l.lwz r6,PT_GPR6(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) l.lwz r7,PT_GPR7(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) l.j _syscall_check_trace_enter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) l.lwz r8,PT_GPR8(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) _restore_all:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #ifdef CONFIG_TRACE_IRQFLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) l.lwz r4,PT_SR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) l.andi r3,r4,(SPR_SR_IEE|SPR_SR_TEE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) l.sfeq r3,r0 /* skip trace if irqs were off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) l.bf skip_hardirqs_on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) TRACE_IRQS_ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) skip_hardirqs_on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) RESTORE_ALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* This returns to userspace code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ENTRY(_ret_from_intr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ENTRY(_ret_from_exception)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) l.lwz r4,PT_SR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) l.andi r3,r4,SPR_SR_SM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) l.sfeqi r3,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) l.bnf _restore_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) l.j _resume_userspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ENTRY(ret_from_fork)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) l.jal schedule_tail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* Check if we are a kernel thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) l.sfeqi r20,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) l.bf 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* ...we are a kernel thread so invoke the requested callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) l.jalr r20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) l.or r3,r22,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* _syscall_returns expect r11 to contain return value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) l.lwz r11,PT_GPR11(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* The syscall fast path return expects call-saved registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * r12-r28 to be untouched, so we restore them here as they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * will have been effectively clobbered when arriving here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * via the call to switch()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) l.lwz r12,PT_GPR12(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) l.lwz r14,PT_GPR14(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) l.lwz r16,PT_GPR16(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) l.lwz r18,PT_GPR18(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) l.lwz r20,PT_GPR20(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) l.lwz r22,PT_GPR22(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) l.lwz r24,PT_GPR24(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) l.lwz r26,PT_GPR26(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) l.lwz r28,PT_GPR28(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) l.j _syscall_return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* ========================================================[ switch ] === */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * This routine switches between two different tasks. The process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * state of one is saved on its kernel stack. Then the state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * of the other is restored from its kernel stack. The memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * management hardware is updated to the second process's state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * Finally, we can return to the second process, via the 'return'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * Note: there are two ways to get to the "going out" portion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * of this code; either by coming in via the entry (_switch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * or via "fork" which must set up an environment equivalent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * to the "_switch" path. If you change this (or in particular, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * SAVE_REGS macro), you'll have to change the fork code also.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* _switch MUST never lay on page boundry, cause it runs from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * effective addresses and beeing interrupted by iTLB miss would kill it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * dTLB miss seams to never accour in the bad place since data accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * are from task structures which are always page aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * The problem happens in RESTORE_ALL_NO_R11 where we first set the EPCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * register, then load the previous register values and only at the end call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * the l.rfe instruction. If get TLB miss in beetwen the EPCR register gets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * garbled and we end up calling l.rfe with the wrong EPCR. (same probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * holds for ESR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * To avoid this problems it is sufficient to align _switch to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * some nice round number smaller than it's size...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* ABI rules apply here... we either enter _switch via schedule() or via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * an imaginary call to which we shall return at return_from_fork. Either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * way, we are a function call and only need to preserve the callee-saved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * registers when we return. As such, we don't need to save the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * on the stack that we won't be returning as they were...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .align 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ENTRY(_switch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* We don't store SR as _switch only gets called in a context where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * the SR will be the same going in and coming out... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* Set up new pt_regs struct for saving task state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) l.addi r1,r1,-(INT_FRAME_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /* No need to store r1/PT_SP as it goes into KSP below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) l.sw PT_GPR2(r1),r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) l.sw PT_GPR9(r1),r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * and expects r12 to be callee-saved... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) l.sw PT_GPR12(r1),r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) l.sw PT_GPR14(r1),r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) l.sw PT_GPR16(r1),r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) l.sw PT_GPR18(r1),r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) l.sw PT_GPR20(r1),r20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) l.sw PT_GPR22(r1),r22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) l.sw PT_GPR24(r1),r24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) l.sw PT_GPR26(r1),r26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) l.sw PT_GPR28(r1),r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) l.sw PT_GPR30(r1),r30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) l.addi r11,r10,0 /* Save old 'current' to 'last' return value*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* We use thread_info->ksp for storing the address of the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * structure so that we can get back to it later... we don't want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * to lose the value of thread_info->ksp, though, so store it as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * pt_regs->sp so that we can easily restore it when we are made
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * live again...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* Save the old value of thread_info->ksp as pt_regs->sp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) l.lwz r29,TI_KSP(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) l.sw PT_SP(r1),r29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /* Swap kernel stack pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) l.sw TI_KSP(r10),r1 /* Save old stack pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) l.or r10,r4,r0 /* Set up new current_thread_info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) l.lwz r1,TI_KSP(r10) /* Load new stack pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) /* Restore the old value of thread_info->ksp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) l.lwz r29,PT_SP(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) l.sw TI_KSP(r10),r29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* ...and restore the registers, except r11 because the return value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * has already been set above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) l.lwz r2,PT_GPR2(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) l.lwz r9,PT_GPR9(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) /* No need to restore r10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* ...and do not restore r11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * and expects r12 to be callee-saved... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) l.lwz r12,PT_GPR12(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) l.lwz r14,PT_GPR14(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) l.lwz r16,PT_GPR16(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) l.lwz r18,PT_GPR18(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) l.lwz r20,PT_GPR20(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) l.lwz r22,PT_GPR22(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) l.lwz r24,PT_GPR24(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) l.lwz r26,PT_GPR26(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) l.lwz r28,PT_GPR28(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) l.lwz r30,PT_GPR30(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /* Unwind stack to pre-switch state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) l.addi r1,r1,(INT_FRAME_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* Return via the link-register back to where we 'came from', where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * that may be either schedule(), ret_from_fork(), or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * ret_from_kernel_thread(). If we are returning to a new thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * we are expected to have set up the arg to schedule_tail already,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * hence we do so here unconditionally:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) l.lwz r3,TI_TASK(r3) /* Load 'prev' as schedule_tail arg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) l.jr r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /* ==================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /* These all use the delay slot for setting the argument register, so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * jump is always happening after the l.addi instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * These are all just wrappers that don't touch the link-register r9, so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * return from the "real" syscall function will return back to the syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * code that did the l.jal that brought us here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* fork requires that we save all the callee-saved registers because they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * are all effectively clobbered by the call to _switch. Here we store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * all the registers that aren't touched by the syscall fast path and thus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * weren't saved there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) _fork_save_extra_regs_and_call:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) l.sw PT_GPR14(r1),r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) l.sw PT_GPR16(r1),r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) l.sw PT_GPR18(r1),r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) l.sw PT_GPR20(r1),r20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) l.sw PT_GPR22(r1),r22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) l.sw PT_GPR24(r1),r24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) l.sw PT_GPR26(r1),r26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) l.jr r29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) l.sw PT_GPR28(r1),r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ENTRY(__sys_clone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) l.movhi r29,hi(sys_clone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) l.ori r29,r29,lo(sys_clone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) l.j _fork_save_extra_regs_and_call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ENTRY(__sys_clone3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) l.movhi r29,hi(sys_clone3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) l.j _fork_save_extra_regs_and_call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) l.ori r29,r29,lo(sys_clone3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ENTRY(__sys_fork)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) l.movhi r29,hi(sys_fork)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) l.ori r29,r29,lo(sys_fork)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) l.j _fork_save_extra_regs_and_call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ENTRY(sys_rt_sigreturn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) l.jal _sys_rt_sigreturn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) l.addi r3,r1,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) l.sfne r30,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) l.bnf _no_syscall_trace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) l.jal do_syscall_trace_leave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) l.addi r3,r1,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) _no_syscall_trace:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) l.j _resume_userspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) l.nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* This is a catch-all syscall for atomic instructions for the OpenRISC 1000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * The functions takes a variable number of parameters depending on which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * particular flavour of atomic you want... parameter 1 is a flag identifying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * the atomic in question. Currently, this function implements the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * following variants:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * XCHG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * @flag: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * @ptr1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * @ptr2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * Atomically exchange the values in pointers 1 and 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ENTRY(sys_or1k_atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /* FIXME: This ignores r3 and always does an XCHG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) DISABLE_INTERRUPTS(r17,r19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) l.lwz r29,0(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) l.lwz r27,0(r5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) l.sw 0(r4),r27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) l.sw 0(r5),r29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ENABLE_INTERRUPTS(r17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) l.jr r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) l.or r11,r0,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* ============================================================[ EOF ]=== */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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