Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * OpenRISC Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Linux architectural port borrowing liberally from similar works of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * others.  All original copyrights apply as per the original source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * declaration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * OpenRISC implementation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * Copyright (C) Jan Henrik Weinstock <jan.weinstock@rwth-aachen.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * et al.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef __ASM_CACHEFLUSH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define __ASM_CACHEFLUSH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * Helper function for flushing or invalidating entire pages from data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * and instruction caches. SMP needs a little extra work, since we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * to flush the pages on all cpus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) extern void local_dcache_page_flush(struct page *page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) extern void local_icache_page_inv(struct page *page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * Data cache flushing always happen on the local cpu. Instruction cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * invalidations need to be broadcasted to all other cpu in the system in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  * case of SMP configurations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifndef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define dcache_page_flush(page)      local_dcache_page_flush(page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define icache_page_inv(page)        local_icache_page_inv(page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #else  /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define dcache_page_flush(page)      local_dcache_page_flush(page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define icache_page_inv(page)        smp_icache_page_inv(page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) extern void smp_icache_page_inv(struct page *page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  * Synchronizes caches. Whenever a cpu writes executable code to memory, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  * should be called to make sure the processor sees the newly written code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline void sync_icache_dcache(struct page *page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		dcache_page_flush(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	icache_page_inv(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)  * Pages with this bit set need not be flushed/invalidated, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)  * they have not changed since last flush. New pages start with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  * PG_arch_1 not set and are therefore dirty by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PG_dc_clean                  PG_arch_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline void flush_dcache_page(struct page *page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	clear_bit(PG_dc_clean, &page->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define flush_icache_user_page(vma, page, addr, len)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) do {							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	if (vma->vm_flags & VM_EXEC)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		sync_icache_dcache(page);		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <asm-generic/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif /* __ASM_CACHEFLUSH_H */