^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) # For a description of the syntax of this configuration file,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) # see Documentation/kbuild/kconfig-language.rst.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) config OPENRISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) select ARCH_32BIT_OFF_T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) select ARCH_HAS_DMA_SET_UNCACHED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) select ARCH_HAS_DMA_CLEAR_UNCACHED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) select ARCH_HAS_SYNC_DMA_FOR_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) select OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) select OF_EARLY_FLATTREE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) select IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) select HANDLE_DOMAIN_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) select GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) select HAVE_ARCH_TRACEHOOK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) select SPARSE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) select GENERIC_IRQ_CHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) select GENERIC_IRQ_PROBE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) select GENERIC_IRQ_SHOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) select GENERIC_IOMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) select GENERIC_CPU_DEVICES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) select HAVE_UID16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) select GENERIC_ATOMIC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) select GENERIC_CLOCKEVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) select GENERIC_CLOCKEVENTS_BROADCAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) select GENERIC_STRNCPY_FROM_USER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) select GENERIC_STRNLEN_USER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) select GENERIC_SMP_IDLE_THREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) select MODULES_USE_ELF_RELA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) select HAVE_DEBUG_STACKOVERFLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) select OR1K_PIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) select ARCH_USE_QUEUED_SPINLOCKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) select ARCH_USE_QUEUED_RWLOCKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) select OMPIC if SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) select ARCH_WANT_FRAME_POINTERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) select GENERIC_IRQ_MULTI_HANDLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) select MMU_GATHER_NO_RANGE if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) select SET_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) config CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) config MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) config GENERIC_HWEIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) config NO_IOPORT_MAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) config TRACE_IRQFLAGS_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) # For now, use generic checksum functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #These can be reimplemented in assembly later if so inclined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) config GENERIC_CSUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) config STACKTRACE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) config LOCKDEP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) menu "Processor type and features"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) prompt "Subarchitecture"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) default OR1K_1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) config OR1K_1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bool "OR1200"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) Generic OpenRISC 1200 architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) config DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bool "Have write through data caches"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) Select this if your implementation features write through data caches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Selecting 'N' here will allow the kernel to force flushing of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) caches at relevant times. Most OpenRISC implementations support write-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) through data caches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) If unsure say N here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) config OPENRISC_BUILTIN_DTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) string "Builtin DTB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) default ""
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) menu "Class II Instructions"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) config OPENRISC_HAVE_INST_FF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bool "Have instruction l.ff1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) Select this if your implementation has the Class II instruction l.ff1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) config OPENRISC_HAVE_INST_FL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bool "Have instruction l.fl1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) Select this if your implementation has the Class II instruction l.fl1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) config OPENRISC_HAVE_INST_MUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) bool "Have instruction l.mul for hardware multiply"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) Select this if your implementation has a hardware multiply instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) config OPENRISC_HAVE_INST_DIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) bool "Have instruction l.div for hardware divide"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) Select this if your implementation has a hardware divide instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) endmenu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) config NR_CPUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int "Maximum number of CPUs (2-32)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) range 2 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) depends on SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) default "2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) config SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) bool "Symmetric Multi-Processing support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) This enables support for systems with more than one CPU. If you have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) a system with only one CPU, say N. If you have a system with more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) than one CPU, say Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) If you don't know what to do here, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) source "kernel/Kconfig.hz"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) config OPENRISC_NO_SPR_SR_DSX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) bool "use SPR_SR_DSX software emulation" if OR1K_1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) SPR_SR_DSX bit is status register bit indicating whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) the last exception has happened in delay slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) OpenRISC architecture makes it optional to have it implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) in hardware and the OR1200 does not have it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) Say N here if you know that your OpenRISC processor has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) SPR_SR_DSX bit implemented. Say Y if you are unsure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) config OPENRISC_HAVE_SHADOW_GPRS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) bool "Support for shadow gpr files" if !SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) default y if SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) Say Y here if your OpenRISC processor features shadowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) register files. They will in such case be used as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) scratch reg storage on exception entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) On SMP systems, this feature is mandatory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) On a unicore system it's safe to say N here if you are unsure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) config CMDLINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) string "Default kernel command string"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) default ""
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) On some architectures there is currently no way for the boot loader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) to pass arguments to the kernel. For these architectures, you should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) supply some command-line options at build time by entering them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) menu "Debugging options"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) config JUMP_UPON_UNHANDLED_EXCEPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bool "Try to die gracefully"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) Now this puts kernel into infinite loop after first oops. Till
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) your kernel crashes this doesn't have any influence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) Say Y if you are unsure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) config OPENRISC_ESR_EXCEPTION_BUG_CHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) bool "Check for possible ESR exception bug"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) This option enables some checks that might expose some problems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) in kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) Say N if you are unsure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) endmenu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) endmenu
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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