^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Nios2 TLB handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2009, Wind River Systems Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pagemap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/tlb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/cpuinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TLB_INDEX_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ((((1UL << (cpuinfo.tlb_ptr_sz - cpuinfo.tlb_num_ways_log2))) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) << PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static void get_misc_and_pid(unsigned long *misc, unsigned long *pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *misc = RDCTL(CTL_TLBMISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *misc &= (TLBMISC_PID | TLBMISC_WAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *pid = *misc & TLBMISC_PID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * This provides a PTEADDR value for addr that will cause a TLB miss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * (fast TLB miss). TLB invalidation replaces entries with this value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static unsigned long pteaddr_invalid(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return ((addr | 0xC0000000UL) >> PAGE_SHIFT) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * This one is only used for pages with the global bit set so we don't care
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * much about the ASID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void replace_tlb_one_pid(unsigned long addr, unsigned long mmu_pid, unsigned long tlbacc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int way;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long org_misc, pid_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* remember pid/way until we return. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) get_misc_and_pid(&org_misc, &pid_misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) WRCTL(CTL_PTEADDR, (addr >> PAGE_SHIFT) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long pteaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long tlbmisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned long pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) WRCTL(CTL_TLBMISC, tlbmisc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pteaddr = RDCTL(CTL_PTEADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (((pteaddr >> 2) & 0xfffff) != (addr >> PAGE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) tlbmisc = RDCTL(CTL_TLBMISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pid = (tlbmisc >> TLBMISC_PID_SHIFT) & TLBMISC_PID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (pid != mmu_pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) tlbmisc = (mmu_pid << TLBMISC_PID_SHIFT) | TLBMISC_WE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) (way << TLBMISC_WAY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) WRCTL(CTL_TLBMISC, tlbmisc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (tlbacc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) WRCTL(CTL_TLBACC, tlbacc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * There should be only a single entry that maps a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * particular {address,pid} so break after a match.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) WRCTL(CTL_TLBMISC, org_misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void flush_tlb_one_pid(unsigned long addr, unsigned long mmu_pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pr_debug("Flush tlb-entry for vaddr=%#lx\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) replace_tlb_one_pid(addr, mmu_pid, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void reload_tlb_one_pid(unsigned long addr, unsigned long mmu_pid, pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pr_debug("Reload tlb-entry for vaddr=%#lx\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) replace_tlb_one_pid(addr, mmu_pid, pte_val(pte));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long mmu_pid = get_pid_from_context(&vma->vm_mm->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) while (start < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) flush_tlb_one_pid(start, mmu_pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) start += PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void reload_tlb_page(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned long mmu_pid = get_pid_from_context(&vma->vm_mm->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) reload_tlb_one_pid(addr, mmu_pid, pte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * This one is only used for pages with the global bit set so we don't care
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * much about the ASID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void flush_tlb_one(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int way;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned long org_misc, pid_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pr_debug("Flush tlb-entry for vaddr=%#lx\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* remember pid/way until we return. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) get_misc_and_pid(&org_misc, &pid_misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) WRCTL(CTL_PTEADDR, (addr >> PAGE_SHIFT) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long pteaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long tlbmisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) WRCTL(CTL_TLBMISC, tlbmisc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pteaddr = RDCTL(CTL_PTEADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (((pteaddr >> 2) & 0xfffff) != (addr >> PAGE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pr_debug("Flush entry by writing way=%dl pid=%ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) way, (pid_misc >> TLBMISC_PID_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) tlbmisc = TLBMISC_WE | (way << TLBMISC_WAY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) WRCTL(CTL_TLBMISC, tlbmisc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) WRCTL(CTL_TLBACC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) WRCTL(CTL_TLBMISC, org_misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void flush_tlb_kernel_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) while (start < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) flush_tlb_one(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) start += PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void dump_tlb_line(unsigned long line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int way;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long org_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pr_debug("dump tlb-entries for line=%#lx (addr %08lx)\n", line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) line << (PAGE_SHIFT + cpuinfo.tlb_num_ways_log2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* remember pid/way until we return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) org_misc = (RDCTL(CTL_TLBMISC) & (TLBMISC_PID | TLBMISC_WAY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) WRCTL(CTL_PTEADDR, line << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned long pteaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned long tlbmisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long tlbacc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) WRCTL(CTL_TLBMISC, TLBMISC_RD | (way << TLBMISC_WAY_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pteaddr = RDCTL(CTL_PTEADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) tlbmisc = RDCTL(CTL_TLBMISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) tlbacc = RDCTL(CTL_TLBACC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if ((tlbacc << PAGE_SHIFT) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pr_debug("-- way:%02x vpn:0x%08lx phys:0x%08lx pid:0x%02lx flags:%c%c%c%c%c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) way,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) (pteaddr << (PAGE_SHIFT-2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) (tlbacc << PAGE_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ((tlbmisc >> TLBMISC_PID_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) TLBMISC_PID_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) (tlbacc & _PAGE_READ ? 'r' : '-'),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) (tlbacc & _PAGE_WRITE ? 'w' : '-'),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) (tlbacc & _PAGE_EXEC ? 'x' : '-'),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) (tlbacc & _PAGE_GLOBAL ? 'g' : '-'),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) (tlbacc & _PAGE_CACHED ? 'c' : '-'));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) WRCTL(CTL_TLBMISC, org_misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void dump_tlb(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) for (i = 0; i < cpuinfo.tlb_num_lines; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dump_tlb_line(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void flush_tlb_pid(unsigned long mmu_pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned long addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned int line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned int way;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned long org_misc, pid_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* remember pid/way until we return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) get_misc_and_pid(&org_misc, &pid_misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) for (line = 0; line < cpuinfo.tlb_num_lines; line++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned long tlbmisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned long pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) WRCTL(CTL_TLBMISC, tlbmisc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) tlbmisc = RDCTL(CTL_TLBMISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pid = (tlbmisc >> TLBMISC_PID_SHIFT) & TLBMISC_PID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (pid != mmu_pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) tlbmisc = TLBMISC_WE | (way << TLBMISC_WAY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) WRCTL(CTL_TLBMISC, tlbmisc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) WRCTL(CTL_TLBACC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) addr += PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) WRCTL(CTL_TLBMISC, org_misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * All entries common to a mm share an asid. To effectively flush these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * entries, we just bump the asid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void flush_tlb_mm(struct mm_struct *mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (current->mm == mm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned long mmu_pid = get_pid_from_context(&mm->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) flush_tlb_pid(mmu_pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) memset(&mm->context, 0, sizeof(mm_context_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) void flush_tlb_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned long addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned int line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned int way;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned long org_misc, pid_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* remember pid/way until we return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) get_misc_and_pid(&org_misc, &pid_misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Start at way 0, way is auto-incremented after each TLBACC write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) WRCTL(CTL_TLBMISC, TLBMISC_WE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Map each TLB entry to physcal address 0 with no-access and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) bad ptbase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) for (line = 0; line < cpuinfo.tlb_num_lines; line++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) for (way = 0; way < cpuinfo.tlb_num_ways; way++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) WRCTL(CTL_TLBACC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) addr += PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* restore pid/way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) WRCTL(CTL_TLBMISC, org_misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) void set_mmu_pid(unsigned long pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned long tlbmisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) tlbmisc = RDCTL(CTL_TLBMISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) tlbmisc = (tlbmisc & TLBMISC_WAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) tlbmisc |= (pid & TLBMISC_PID_MASK) << TLBMISC_PID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) WRCTL(CTL_TLBMISC, tlbmisc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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