Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _ASM_NIOS2_REGISTERS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _ASM_NIOS2_REGISTERS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/cpuinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* control register numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CTL_FSTATUS	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CTL_ESTATUS	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CTL_BSTATUS	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CTL_IENABLE	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CTL_IPENDING	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CTL_CPUID	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CTL_RSV1	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CTL_EXCEPTION	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CTL_PTEADDR	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CTL_TLBACC	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CTL_TLBMISC	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CTL_RSV2	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CTL_BADADDR	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CTL_CONFIG	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CTL_MPUBASE	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CTL_MPUACC	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* access control registers using GCC builtins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RDCTL(r)	__builtin_rdctl(r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define WRCTL(r, v)	__builtin_wrctl(r, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* status register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define STATUS_PIE	(1 << 0)	/* processor interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define STATUS_U	(1 << 1)	/* user mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define STATUS_EH	(1 << 2)	/* Exception mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* estatus register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ESTATUS_EPIE	(1 << 0)	/* processor interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ESTATUS_EU	(1 << 1)	/* user mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ESTATUS_EH	(1 << 2)	/* Exception mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* tlbmisc register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TLBMISC_PID_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TLBMISC_PID_MASK	((1UL << cpuinfo.tlb_pid_num_bits) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TLBMISC_WAY_MASK	0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TLBMISC_WAY_SHIFT	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TLBMISC_PID	(TLBMISC_PID_MASK << TLBMISC_PID_SHIFT)	/* TLB PID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TLBMISC_WE	(1 << 18)	/* TLB write enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TLBMISC_RD	(1 << 19)	/* TLB read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TLBMISC_WAY	(TLBMISC_WAY_MASK << TLBMISC_WAY_SHIFT) /* TLB way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif /* _ASM_NIOS2_REGISTERS_H */