^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Macro used to simplify coding multi-line assembler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Some of the bit test macro can simplify down to one line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * depending on the mask value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2004 Microtronix Datacom Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _ASM_NIOS2_ASMMACROS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _ASM_NIOS2_ASMMACROS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * ANDs reg2 with mask and places the result in reg1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * You cannnot use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) .macro ANDI32 reg1, reg2, mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .if \mask & 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .if \mask & 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) movhi \reg1, %hi(\mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) movui \reg1, %lo(\mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) and \reg1, \reg1, \reg2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) andi \reg1, \reg2, %lo(\mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) andhi \reg1, \reg2, %hi(\mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * ORs reg2 with mask and places the result in reg1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * It is safe to use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .macro ORI32 reg1, reg2, mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .if \mask & 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .if \mask & 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) orhi \reg1, \reg2, %hi(\mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ori \reg1, \reg2, %lo(\mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ori \reg1, \reg2, %lo(\mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) orhi \reg1, \reg2, %hi(\mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * XORs reg2 with mask and places the result in reg1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * It is safe to use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .macro XORI32 reg1, reg2, mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .if \mask & 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .if \mask & 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) xorhi \reg1, \reg2, %hi(\mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) xori \reg1, \reg1, %lo(\mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) xori \reg1, \reg2, %lo(\mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) xorhi \reg1, \reg2, %hi(\mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * This is a support macro for BTBZ & BTBNZ. It checks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * the bit to make sure it is valid 32 value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * It is safe to use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .macro BT reg1, reg2, bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .if \bit > 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .if \bit < 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) andi \reg1, \reg2, (1 << \bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) andhi \reg1, \reg2, (1 << (\bit - 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Tests the bit in reg2 and branches to label if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * bit is zero. The result of the bit test is stored in reg1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * It is safe to use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .macro BTBZ reg1, reg2, bit, label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) BT \reg1, \reg2, \bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) beq \reg1, r0, \label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Tests the bit in reg2 and branches to label if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * bit is non-zero. The result of the bit test is stored in reg1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * It is safe to use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .macro BTBNZ reg1, reg2, bit, label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) BT \reg1, \reg2, \bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bne \reg1, r0, \label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Tests the bit in reg2 and then compliments the bit in reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * The result of the bit test is stored in reg1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * It is NOT safe to use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .macro BTC reg1, reg2, bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .if \bit > 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .if \bit < 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) andi \reg1, \reg2, (1 << \bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) xori \reg2, \reg2, (1 << \bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) andhi \reg1, \reg2, (1 << (\bit - 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) xorhi \reg2, \reg2, (1 << (\bit - 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Tests the bit in reg2 and then sets the bit in reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * The result of the bit test is stored in reg1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * It is NOT safe to use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .macro BTS reg1, reg2, bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .if \bit > 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .if \bit < 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) andi \reg1, \reg2, (1 << \bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ori \reg2, \reg2, (1 << \bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) andhi \reg1, \reg2, (1 << (\bit - 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) orhi \reg2, \reg2, (1 << (\bit - 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Tests the bit in reg2 and then resets the bit in reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * The result of the bit test is stored in reg1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * It is NOT safe to use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .macro BTR reg1, reg2, bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .if \bit > 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .if \bit < 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) andi \reg1, \reg2, (1 << \bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) andi \reg2, \reg2, %lo(~(1 << \bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) andhi \reg1, \reg2, (1 << (\bit - 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) andhi \reg2, \reg2, %lo(~(1 << (\bit - 16)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Tests the bit in reg2 and then compliments the bit in reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * The result of the bit test is stored in reg1. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * original bit was zero it branches to label.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * It is NOT safe to use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .macro BTCBZ reg1, reg2, bit, label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) BTC \reg1, \reg2, \bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) beq \reg1, r0, \label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Tests the bit in reg2 and then compliments the bit in reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * The result of the bit test is stored in reg1. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * original bit was non-zero it branches to label.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * It is NOT safe to use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .macro BTCBNZ reg1, reg2, bit, label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) BTC \reg1, \reg2, \bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) bne \reg1, r0, \label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Tests the bit in reg2 and then sets the bit in reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * The result of the bit test is stored in reg1. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * original bit was zero it branches to label.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * It is NOT safe to use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .macro BTSBZ reg1, reg2, bit, label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) BTS \reg1, \reg2, \bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) beq \reg1, r0, \label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Tests the bit in reg2 and then sets the bit in reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * The result of the bit test is stored in reg1. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * original bit was non-zero it branches to label.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * It is NOT safe to use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .macro BTSBNZ reg1, reg2, bit, label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) BTS \reg1, \reg2, \bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) bne \reg1, r0, \label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Tests the bit in reg2 and then resets the bit in reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * The result of the bit test is stored in reg1. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * original bit was zero it branches to label.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * It is NOT safe to use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .macro BTRBZ reg1, reg2, bit, label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) BTR \reg1, \reg2, \bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bne \reg1, r0, \label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Tests the bit in reg2 and then resets the bit in reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * The result of the bit test is stored in reg1. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * original bit was non-zero it branches to label.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * It is NOT safe to use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .macro BTRBNZ reg1, reg2, bit, label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) BTR \reg1, \reg2, \bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) bne \reg1, r0, \label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Tests the bits in mask against reg2 stores the result in reg1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * If the all the bits in the mask are zero it branches to label.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * It is safe to use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .macro TSTBZ reg1, reg2, mask, label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ANDI32 \reg1, \reg2, \mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) beq \reg1, r0, \label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * Tests the bits in mask against reg2 stores the result in reg1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * If the any of the bits in the mask are 1 it branches to label.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * It is safe to use the same register for reg1 & reg2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .macro TSTBNZ reg1, reg2, mask, label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ANDI32 \reg1, \reg2, \mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) bne \reg1, r0, \label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Pushes reg onto the stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .macro PUSH reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) addi sp, sp, -4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) stw \reg, 0(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Pops the top of the stack into reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .macro POP reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ldw \reg, 0(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) addi sp, sp, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #endif /* _ASM_NIOS2_ASMMACROS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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