^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2008-2010 Thomas Chou <thomas@wytron.com.tw>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #if (defined(CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE) && defined(JTAG_UART_BASE))\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) || (defined(CONFIG_SERIAL_ALTERA_UART_CONSOLE) && defined(UART0_BASE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) static void *my_ioremap(unsigned long physaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) return (void *)(physaddr | CONFIG_NIOS2_IO_REGION_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #if defined(CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE) && defined(JTAG_UART_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ALTERA_JTAGUART_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ALTERA_JTAGUART_DATA_REG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ALTERA_JTAGUART_CONTROL_REG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ALTERA_JTAGUART_CONTROL_AC_MSK (0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ALTERA_JTAGUART_CONTROL_WSPACE_MSK (0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static void *uartbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #if defined(CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static void jtag_putc(int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) if (readl(uartbase + ALTERA_JTAGUART_CONTROL_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ALTERA_JTAGUART_CONTROL_WSPACE_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) writeb(ch, uartbase + ALTERA_JTAGUART_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static void jtag_putc(int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) while ((readl(uartbase + ALTERA_JTAGUART_CONTROL_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ALTERA_JTAGUART_CONTROL_WSPACE_MSK) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) writeb(ch, uartbase + ALTERA_JTAGUART_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int putchar(int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) jtag_putc(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) uartbase = my_ioremap((unsigned long) JTAG_UART_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) writel(ALTERA_JTAGUART_CONTROL_AC_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) uartbase + ALTERA_JTAGUART_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #elif defined(CONFIG_SERIAL_ALTERA_UART_CONSOLE) && defined(UART0_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ALTERA_UART_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ALTERA_UART_TXDATA_REG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ALTERA_UART_STATUS_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ALTERA_UART_DIVISOR_REG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ALTERA_UART_STATUS_TRDY_MSK (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static unsigned uartbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void uart_putc(int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) for (i = 0; (i < 0x10000); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (readw(uartbase + ALTERA_UART_STATUS_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ALTERA_UART_STATUS_TRDY_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) writeb(ch, uartbase + ALTERA_UART_TXDATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int putchar(int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) uart_putc(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (ch == '\n')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) uart_putc('\r');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned int baud, baudclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) uartbase = (unsigned long) my_ioremap((unsigned long) UART0_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) baud = CONFIG_SERIAL_ALTERA_UART_BAUDRATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) baudclk = UART0_FREQ / baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writew(baudclk, uartbase + ALTERA_UART_DIVISOR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int putchar(int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int puts(const char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) while (*s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) putchar(*s++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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