Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) // Copyright (C) 2005-2017 Andes Technology Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <asm/nds32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/l2_cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <nds32_intrinsic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/cache_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) extern struct cache_info L1_cache_info[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) int va_kernel_present(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	pmd_t *pmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	pte_t *ptep, pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	pmd = pmd_off_k(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	if (!pmd_none(*pmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		ptep = pte_offset_map(pmd, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		pte = *ptep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		if (pte_present(pte))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 			return pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) pte_t va_present(struct mm_struct * mm, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	pgd_t *pgd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	p4d_t *p4d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	pud_t *pud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	pmd_t *pmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	pte_t *ptep, pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	pgd = pgd_offset(mm, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	if (!pgd_none(*pgd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		p4d = p4d_offset(pgd, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		if (!p4d_none(*p4d)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			pud = pud_offset(p4d, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 			if (!pud_none(*pud)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 				pmd = pmd_offset(pud, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 				if (!pmd_none(*pmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 					ptep = pte_offset_map(pmd, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 					pte = *ptep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 					if (pte_present(pte))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 						return pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 				}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) int va_readable(struct pt_regs *regs, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct mm_struct *mm = current->mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	pte_t pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	if (user_mode(regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		/* user mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		pte = va_present(mm, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		if (!pte && pte_read(pte))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		/* superuser mode is always readable, so we can only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		 * check it is present or not*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		return (! !va_kernel_present(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) int va_writable(struct pt_regs *regs, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct mm_struct *mm = current->mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	pte_t pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (user_mode(regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		/* user mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		pte = va_present(mm, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		if (!pte && pte_write(pte))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		/* superuser mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		pte = va_kernel_present(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		if (!pte && pte_kernel_write(pte))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * All
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void cpu_icache_inval_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	unsigned long end, line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	line_size = L1_cache_info[ICACHE].line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	end =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	    line_size * L1_cache_info[ICACHE].ways * L1_cache_info[ICACHE].sets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	} while (end > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	__nds32__isb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void cpu_dcache_inval_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	__nds32__cctl_l1d_invalall();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #ifdef CONFIG_CACHE_L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void dcache_wb_all_level(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned long flags, cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	__nds32__cctl_l1d_wball_alvl();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* Section 1: Ensure the section 2 & 3 program code execution after */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	__nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	/* Section 2: Confirm the writeback all level is done in CPU and L2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	cmd = CCTL_CMD_L2_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	L2_CMD_RDY();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	L2C_W_REG(L2_CCTL_CMD_OFF, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	L2_CMD_RDY();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	/* Section 3: Writeback whole L2 cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	cmd = CCTL_ALL_CMD | CCTL_CMD_L2_IX_WB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	L2_CMD_RDY();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	L2C_W_REG(L2_CCTL_CMD_OFF, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	L2_CMD_RDY();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	__nds32__msync_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) EXPORT_SYMBOL(dcache_wb_all_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void cpu_dcache_wb_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	__nds32__cctl_l1d_wball_one_lvl();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	__nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void cpu_dcache_wbinval_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	cpu_dcache_wb_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	cpu_dcache_inval_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  * Page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void cpu_icache_inval_page(unsigned long start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	unsigned long line_size, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	line_size = L1_cache_info[ICACHE].line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	end = start + PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	} while (end != start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	__nds32__isb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void cpu_dcache_inval_page(unsigned long start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	unsigned long line_size, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	line_size = L1_cache_info[DCACHE].line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	end = start + PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	} while (end != start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) void cpu_dcache_wb_page(unsigned long start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	unsigned long line_size, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	line_size = L1_cache_info[DCACHE].line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	end = start + PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	} while (end != start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	__nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) void cpu_dcache_wbinval_page(unsigned long start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	unsigned long line_size, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	line_size = L1_cache_info[DCACHE].line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	end = start + PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		end -= line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	} while (end != start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	__nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) void cpu_cache_wbinval_page(unsigned long page, int flushi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	cpu_dcache_wbinval_page(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (flushi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		cpu_icache_inval_page(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  * Range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) void cpu_icache_inval_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	unsigned long line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	line_size = L1_cache_info[ICACHE].line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	while (end > start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		start += line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	__nds32__isb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void cpu_dcache_inval_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	unsigned long line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	line_size = L1_cache_info[DCACHE].line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	while (end > start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		start += line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) void cpu_dcache_wb_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	unsigned long line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	line_size = L1_cache_info[DCACHE].line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	while (end > start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		start += line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	__nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) void cpu_dcache_wbinval_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	unsigned long line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	line_size = L1_cache_info[DCACHE].line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	while (end > start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		start += line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	__nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) void cpu_cache_wbinval_range(unsigned long start, unsigned long end, int flushi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	unsigned long line_size, align_start, align_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	line_size = L1_cache_info[DCACHE].line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	align_start = start & ~(line_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	align_end = (end + line_size - 1) & ~(line_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	cpu_dcache_wbinval_range(align_start, align_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (flushi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		line_size = L1_cache_info[ICACHE].line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		align_start = start & ~(line_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		align_end = (end + line_size - 1) & ~(line_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		cpu_icache_inval_range(align_start, align_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) void cpu_cache_wbinval_range_check(struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 				   unsigned long start, unsigned long end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 				   bool flushi, bool wbd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	unsigned long line_size, t_start, t_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	if (!flushi && !wbd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	line_size = L1_cache_info[DCACHE].line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	start = start & ~(line_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	end = (end + line_size - 1) & ~(line_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if ((end - start) > (8 * PAGE_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		if (wbd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			cpu_dcache_wbinval_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		if (flushi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			cpu_icache_inval_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	t_start = (start + PAGE_SIZE) & PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	t_end = ((end - 1) & PAGE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	if ((start & PAGE_MASK) == t_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		if (va_present(vma->vm_mm, start)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			if (wbd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 				cpu_dcache_wbinval_range(start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			if (flushi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 				cpu_icache_inval_range(start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (va_present(vma->vm_mm, start)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		if (wbd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			cpu_dcache_wbinval_range(start, t_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		if (flushi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			cpu_icache_inval_range(start, t_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	if (va_present(vma->vm_mm, end - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		if (wbd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 			cpu_dcache_wbinval_range(t_end, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		if (flushi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 			cpu_icache_inval_range(t_end, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	while (t_start < t_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		if (va_present(vma->vm_mm, t_start)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 			if (wbd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 				cpu_dcache_wbinval_page(t_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 			if (flushi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 				cpu_icache_inval_page(t_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		t_start += PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #ifdef CONFIG_CACHE_L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static inline void cpu_l2cache_op(unsigned long start, unsigned long end, unsigned long op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	if (atl2c_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		unsigned long p_start = __pa(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		unsigned long p_end = __pa(end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		unsigned long cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		unsigned long line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		/* TODO Can Use PAGE Mode to optimize if range large than PAGE_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		line_size = L2_CACHE_LINE_SIZE();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		p_start = p_start & (~(line_size - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		p_end = (p_end + line_size - 1) & (~(line_size - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		cmd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		    (p_start & ~(line_size - 1)) | op |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		    CCTL_SINGLE_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 			L2_CMD_RDY();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 			L2C_W_REG(L2_CCTL_CMD_OFF, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 			cmd += line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 			p_start += line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		} while (p_end > p_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		cmd = CCTL_CMD_L2_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		L2_CMD_RDY();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		L2C_W_REG(L2_CCTL_CMD_OFF, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		L2_CMD_RDY();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define cpu_l2cache_op(start,end,op) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)  * DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) void cpu_dma_wb_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	unsigned long line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	line_size = L1_cache_info[DCACHE].line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	start = start & (~(line_size - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	end = (end + line_size - 1) & (~(line_size - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	if (unlikely(start == end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	cpu_dcache_wb_range(start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_WB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	__nds32__msync_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) void cpu_dma_inval_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	unsigned long line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	unsigned long old_start = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	unsigned long old_end = end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	line_size = L1_cache_info[DCACHE].line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	start = start & (~(line_size - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	end = (end + line_size - 1) & (~(line_size - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	if (unlikely(start == end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	if (start != old_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		cpu_dcache_wbinval_range(start, start + line_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		cpu_l2cache_op(start, start + line_size, CCTL_CMD_L2_PA_WBINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	if (end != old_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		cpu_dcache_wbinval_range(end - line_size, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		cpu_l2cache_op(end - line_size, end, CCTL_CMD_L2_PA_WBINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	cpu_dcache_inval_range(start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_INVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	__nds32__msync_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) void cpu_dma_wbinval_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	unsigned long line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	line_size = L1_cache_info[DCACHE].line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	start = start & (~(line_size - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	end = (end + line_size - 1) & (~(line_size - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	if (unlikely(start == end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	cpu_dcache_wbinval_range(start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_WBINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	__nds32__msync_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) void cpu_proc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) void cpu_proc_fin(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) void cpu_do_idle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	__nds32__standby_no_wake_grant();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) void cpu_reset(unsigned long reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	GIE_DISABLE();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	tmp &= ~(CACHE_CTL_mskIC_EN | CACHE_CTL_mskDC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	__nds32__mtsr_isb(tmp, NDS32_SR_CACHE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	cpu_dcache_wbinval_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	cpu_icache_inval_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	__asm__ __volatile__("jr.toff %0\n\t"::"r"(reset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) void cpu_switch_mm(struct mm_struct *mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	unsigned long cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	cid = __nds32__mfsr(NDS32_SR_TLB_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	cid = (cid & ~TLB_MISC_mskCID) | mm->context.id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	__nds32__mtsr_dsb(cid, NDS32_SR_TLB_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	__nds32__mtsr_isb(__pa(mm->pgd), NDS32_SR_L1_PPTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }