^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) 2005-2017 Andes Technology Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/sysctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define DEBUG(enable, tagged, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) do{ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) if (enable) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) if (tagged) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) pr_warn("[ %30s() ] ", __func__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) pr_warn(__VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RT(inst) (((inst) >> 20) & 0x1FUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RA(inst) (((inst) >> 15) & 0x1FUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RB(inst) (((inst) >> 10) & 0x1FUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SV(inst) (((inst) >> 8) & 0x3UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMM(inst) (((inst) >> 0) & 0x7FFFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RA3(inst) (((inst) >> 3) & 0x7UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RT3(inst) (((inst) >> 6) & 0x7UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMM3U(inst) (((inst) >> 0) & 0x7UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RA5(inst) (((inst) >> 0) & 0x1FUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RT4(inst) (((inst) >> 5) & 0xFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GET_IMMSVAL(imm_value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) (((imm_value >> 14) & 0x1) ? (imm_value - 0x8000) : imm_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define __get8_data(val,addr,err) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) __asm__( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "1: lbi.bi %1, [%2], #1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "2:\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) " .pushsection .text.fixup,\"ax\"\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) " .align 2\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "3: movi %0, #1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) " j 2b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) " .popsection\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) " .pushsection __ex_table,\"a\"\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) " .align 3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) " .long 1b, 3b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) " .popsection\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) : "=r" (err), "=&r" (val), "=r" (addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) : "0" (err), "2" (addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define get16_data(addr, val_ptr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int err = 0, v, a = addr; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) __get8_data(v,a,err); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *val_ptr = v << 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) __get8_data(v,a,err); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *val_ptr |= v << 8; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (err) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) goto fault; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *val_ptr = le16_to_cpu(*val_ptr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define get32_data(addr, val_ptr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int err = 0, v, a = addr; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __get8_data(v,a,err); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *val_ptr = v << 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __get8_data(v,a,err); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *val_ptr |= v << 8; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __get8_data(v,a,err); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *val_ptr |= v << 16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __get8_data(v,a,err); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *val_ptr |= v << 24; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (err) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) goto fault; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *val_ptr = le32_to_cpu(*val_ptr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define get_data(addr, val_ptr, len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (len == 2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) get16_data(addr, val_ptr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) get32_data(addr, val_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define set16_data(addr, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned int err = 0, *ptr = addr ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) val = le32_to_cpu(val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __asm__( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "1: sbi.bi %2, [%1], #1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) " srli %2, %2, #8\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "2: sbi %2, [%1]\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "3:\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) " .pushsection .text.fixup,\"ax\"\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) " .align 2\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "4: movi %0, #1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) " j 3b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) " .popsection\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) " .pushsection __ex_table,\"a\"\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) " .align 3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) " .long 1b, 4b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) " .long 2b, 4b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) " .popsection\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) : "=r" (err), "+r" (ptr), "+r" (val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) : "0" (err) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (err) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) goto fault; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define set32_data(addr, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int err = 0, *ptr = addr ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) val = le32_to_cpu(val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __asm__( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "1: sbi.bi %2, [%1], #1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) " srli %2, %2, #8\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "2: sbi.bi %2, [%1], #1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) " srli %2, %2, #8\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "3: sbi.bi %2, [%1], #1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) " srli %2, %2, #8\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "4: sbi %2, [%1]\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "5:\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) " .pushsection .text.fixup,\"ax\"\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) " .align 2\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "6: movi %0, #1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) " j 5b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) " .popsection\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) " .pushsection __ex_table,\"a\"\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) " .align 3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) " .long 1b, 6b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) " .long 2b, 6b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) " .long 3b, 6b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) " .long 4b, 6b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) " .popsection\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) : "=r" (err), "+r" (ptr), "+r" (val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) : "0" (err) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (err) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) goto fault; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define set_data(addr, val, len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (len == 2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) set16_data(addr, val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) set32_data(addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define NDS32_16BIT_INSTRUCTION 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) extern pte_t va_present(struct mm_struct *mm, unsigned long addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) extern pte_t va_kernel_present(unsigned long addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) extern int va_readable(struct pt_regs *regs, unsigned long addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) extern int va_writable(struct pt_regs *regs, unsigned long addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int unalign_access_mode = 0, unalign_access_debug = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static inline unsigned long *idx_to_addr(struct pt_regs *regs, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* this should be consistent with ptrace.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (idx >= 0 && idx <= 25) /* R0-R25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return ®s->uregs[0] + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) else if (idx >= 28 && idx <= 30) /* FP, GP, LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return ®s->fp + (idx - 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) else if (idx == 31) /* SP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ®s->sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return NULL; /* cause a segfault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static inline unsigned long get_inst(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return be32_to_cpu(get_unaligned((u32 *) addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static inline unsigned long sign_extend(unsigned long val, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned char *s, *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) val = cpu_to_le32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) s = (void *)&val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) t = (void *)&ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) while (i++ < len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *t++ = *s++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (((*(t - 1)) & 0x80) && (i < 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) while (i++ <= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *t++ = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return le32_to_cpu(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static inline int do_16(unsigned long inst, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int imm, regular, load, len, addr_mode, idx_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned long unaligned_addr, target_val, source_idx, target_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) switch ((inst >> 9) & 0x3F) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case 0x12: /* LHI333 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) imm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) regular = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) load = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) addr_mode = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) idx_mode = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) case 0x10: /* LWI333 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) imm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) regular = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) load = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) addr_mode = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) idx_mode = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case 0x11: /* LWI333.bi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) imm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) regular = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) load = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) addr_mode = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) idx_mode = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case 0x1A: /* LWI450 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) imm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) regular = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) load = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) addr_mode = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) idx_mode = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case 0x16: /* SHI333 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) imm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) regular = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) load = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) addr_mode = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) idx_mode = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case 0x14: /* SWI333 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) imm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) regular = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) load = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) addr_mode = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) idx_mode = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case 0x15: /* SWI333.bi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) imm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) regular = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) load = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) addr_mode = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) idx_mode = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case 0x1B: /* SWI450 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) imm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) regular = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) load = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) addr_mode = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) idx_mode = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (addr_mode == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unaligned_addr = *idx_to_addr(regs, RA3(inst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) source_idx = RA3(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unaligned_addr = *idx_to_addr(regs, RA5(inst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) source_idx = RA5(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (idx_mode == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) target_idx = RT3(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) target_idx = RT4(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (imm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) shift = IMM3U(inst) * len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (regular)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unaligned_addr += shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (load) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (!access_ok((void *)unaligned_addr, len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) get_data(unaligned_addr, &target_val, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *idx_to_addr(regs, target_idx) = target_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!access_ok((void *)unaligned_addr, len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) target_val = *idx_to_addr(regs, target_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) set_data((void *)unaligned_addr, target_val, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!regular)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) *idx_to_addr(regs, source_idx) = unaligned_addr + shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) regs->ipc += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static inline int do_32(unsigned long inst, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int imm, regular, load, len, sign_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned long unaligned_addr, target_val, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unaligned_addr = *idx_to_addr(regs, RA(inst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) switch ((inst >> 25) << 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case 0x02: /* LHI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) imm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) regular = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) load = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) sign_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case 0x0A: /* LHI.bi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) imm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) regular = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) load = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) sign_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case 0x22: /* LHSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) imm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) regular = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) load = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) sign_ext = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) case 0x2A: /* LHSI.bi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) imm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) regular = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) load = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) sign_ext = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case 0x04: /* LWI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) imm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) regular = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) load = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) sign_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case 0x0C: /* LWI.bi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) imm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) regular = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) load = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) sign_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case 0x12: /* SHI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) imm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) regular = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) load = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) sign_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case 0x1A: /* SHI.bi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) imm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) regular = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) load = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) sign_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) case 0x14: /* SWI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) imm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) regular = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) load = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) sign_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case 0x1C: /* SWI.bi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) imm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) regular = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) load = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) sign_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) switch (inst & 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case 0x01: /* LH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) imm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) regular = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) load = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) sign_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case 0x05: /* LH.bi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) imm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) regular = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) load = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) sign_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case 0x11: /* LHS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) imm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) regular = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) load = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) sign_ext = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) case 0x15: /* LHS.bi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) imm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) regular = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) load = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) sign_ext = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case 0x02: /* LW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) imm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) regular = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) load = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) sign_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case 0x06: /* LW.bi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) imm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) regular = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) load = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) sign_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case 0x09: /* SH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) imm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) regular = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) load = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) sign_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case 0x0D: /* SH.bi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) imm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) regular = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) load = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) sign_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case 0x0A: /* SW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) imm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) regular = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) load = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) sign_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) case 0x0E: /* SW.bi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) imm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) regular = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) load = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) sign_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (imm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) shift = GET_IMMSVAL(IMM(inst)) * len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) shift = *idx_to_addr(regs, RB(inst)) << SV(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (regular)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unaligned_addr += shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (load) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (!access_ok((void *)unaligned_addr, len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) get_data(unaligned_addr, &target_val, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (sign_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) *idx_to_addr(regs, RT(inst)) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) sign_extend(target_val, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) *idx_to_addr(regs, RT(inst)) = target_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!access_ok((void *)unaligned_addr, len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) target_val = *idx_to_addr(regs, RT(inst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) set_data((void *)unaligned_addr, target_val, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!regular)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) *idx_to_addr(regs, RA(inst)) = unaligned_addr + shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) regs->ipc += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int do_unaligned_access(unsigned long addr, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned long inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) mm_segment_t seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) inst = get_inst(regs->ipc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) DEBUG((unalign_access_debug > 0), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) "Faulting addr: 0x%08lx, pc: 0x%08lx [inst: 0x%08lx ]\n", addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) regs->ipc, inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) seg = force_uaccess_begin();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (inst & NDS32_16BIT_INSTRUCTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret = do_16((inst >> 16) & 0xffff, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = do_32(inst, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) force_uaccess_end(seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static struct ctl_table alignment_tbl[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .procname = "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .data = &unalign_access_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .maxlen = sizeof(unalign_access_mode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .mode = 0666,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .proc_handler = &proc_dointvec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .procname = "debug_info",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .data = &unalign_access_debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .maxlen = sizeof(unalign_access_debug),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .mode = 0644,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .proc_handler = &proc_dointvec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static struct ctl_table nds32_sysctl_table[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .procname = "unaligned_access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .mode = 0555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .child = alignment_tbl},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static struct ctl_path nds32_path[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {.procname = "nds32"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * Initialize nds32 alignment-correction interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static int __init nds32_sysctl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) register_sysctl_paths(nds32_path, nds32_sysctl_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) __initcall(nds32_sysctl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #endif /* CONFIG_PROC_FS */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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