^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) 2005-2018 Andes Technology Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <asm/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/sfp-machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/fpuemu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/nds32_fpu_inst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DPFROMREG(dp, x) (dp = (void *)((unsigned long *)fpu_reg + 2*x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifdef __NDS32_EL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SPFROMREG(sp, x)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ((sp) = (void *)((unsigned long *)fpu_reg + (x^1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SPFROMREG(sp, x) ((sp) = (void *)((unsigned long *)fpu_reg + x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DEF3OP(name, p, f1, f2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) void fpemu_##name##p(void *ft, void *fa, void *fb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) f1(fa, fa, fb); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) f2(ft, ft, fa); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DEF3OPNEG(name, p, f1, f2, f3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) void fpemu_##name##p(void *ft, void *fa, void *fb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) f1(fa, fa, fb); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) f2(ft, ft, fa); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) f3(ft, ft); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DEF3OP(fmadd, s, fmuls, fadds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DEF3OP(fmsub, s, fmuls, fsubs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DEF3OP(fmadd, d, fmuld, faddd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DEF3OP(fmsub, d, fmuld, fsubd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DEF3OPNEG(fnmadd, s, fmuls, fadds, fnegs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DEF3OPNEG(fnmsub, s, fmuls, fsubs, fnegs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEF3OPNEG(fnmadd, d, fmuld, faddd, fnegd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DEF3OPNEG(fnmsub, d, fmuld, fsubd, fnegd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const unsigned char cmptab[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SF_CEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SF_CEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SF_CLT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SF_CLT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SF_CLT | SF_CEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SF_CLT | SF_CEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SF_CUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SF_CUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) enum ARGTYPE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) S1S = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) S2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) S1D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) CS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) D1D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) D2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) D1S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) union func_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void (*t)(void *ft, void *fa, void *fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void (*b)(void *ft, void *fa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Emulate a single FPU arithmetic instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int fpu_emu(struct fpu_struct *fpu_reg, unsigned long insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int rfmt; /* resulting format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) union func_t func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int ftype = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) switch (rfmt = NDS32Insn_OPCODE_COP0(insn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case fs1_op:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) switch (NDS32Insn_OPCODE_BIT69(insn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case fadds_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) func.t = fadds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ftype = S2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case fsubs_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) func.t = fsubs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ftype = S2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case fmadds_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) func.t = fpemu_fmadds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ftype = S2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case fmsubs_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) func.t = fpemu_fmsubs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ftype = S2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case fnmadds_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) func.t = fpemu_fnmadds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ftype = S2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case fnmsubs_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) func.t = fpemu_fnmsubs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ftype = S2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) case fmuls_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) func.t = fmuls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ftype = S2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case fdivs_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) func.t = fdivs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ftype = S2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) case fs1_f2op_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) switch (NDS32Insn_OPCODE_BIT1014(insn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case fs2d_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) func.b = fs2d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ftype = S1D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case fs2si_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) func.b = fs2si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ftype = S1S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case fs2si_z_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) func.b = fs2si_z;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ftype = S1S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case fs2ui_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) func.b = fs2ui;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ftype = S1S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case fs2ui_z_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) func.b = fs2ui_z;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ftype = S1S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case fsi2s_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) func.b = fsi2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ftype = S1S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case fui2s_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) func.b = fui2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ftype = S1S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case fsqrts_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) func.b = fsqrts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ftype = S1S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return SIGILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return SIGILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case fs2_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) switch (NDS32Insn_OPCODE_BIT69(insn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case fcmpeqs_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case fcmpeqs_e_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case fcmplts_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) case fcmplts_e_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) case fcmples_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case fcmples_e_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case fcmpuns_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case fcmpuns_e_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ftype = CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return SIGILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case fd1_op:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) switch (NDS32Insn_OPCODE_BIT69(insn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case faddd_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) func.t = faddd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ftype = D2D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case fsubd_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) func.t = fsubd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ftype = D2D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) case fmaddd_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) func.t = fpemu_fmaddd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ftype = D2D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case fmsubd_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) func.t = fpemu_fmsubd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ftype = D2D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case fnmaddd_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) func.t = fpemu_fnmaddd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ftype = D2D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case fnmsubd_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) func.t = fpemu_fnmsubd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ftype = D2D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case fmuld_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) func.t = fmuld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ftype = D2D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) case fdivd_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) func.t = fdivd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ftype = D2D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case fd1_f2op_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) switch (NDS32Insn_OPCODE_BIT1014(insn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case fd2s_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) func.b = fd2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ftype = D1S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case fd2si_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) func.b = fd2si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ftype = D1S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case fd2si_z_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) func.b = fd2si_z;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ftype = D1S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) case fd2ui_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) func.b = fd2ui;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ftype = D1S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) case fd2ui_z_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) func.b = fd2ui_z;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ftype = D1S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case fsi2d_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) func.b = fsi2d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ftype = D1S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case fui2d_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) func.b = fui2d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ftype = D1S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case fsqrtd_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) func.b = fsqrtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ftype = D1D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return SIGILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return SIGILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case fd2_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) switch (NDS32Insn_OPCODE_BIT69(insn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case fcmpeqd_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case fcmpeqd_e_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case fcmpltd_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case fcmpltd_e_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case fcmpled_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case fcmpled_e_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case fcmpund_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case fcmpund_e_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ftype = CD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return SIGILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return SIGILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) switch (ftype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case S1S:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) void *ft, *fa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) SPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) SPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) func.b(ft, fa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case S2S:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) void *ft, *fa, *fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) SPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) SPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) SPFROMREG(fb, NDS32Insn_OPCODE_Rb(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) func.t(ft, fa, fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case S1D:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) void *ft, *fa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) DPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) SPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) func.b(ft, fa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case CS:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned int cmpop = NDS32Insn_OPCODE_BIT69(insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) void *ft, *fa, *fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) SPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) SPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) SPFROMREG(fb, NDS32Insn_OPCODE_Rb(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (cmpop < 0x8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) cmpop = cmptab[cmpop];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) fcmps(ft, fa, fb, cmpop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return SIGILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case D1D:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) void *ft, *fa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) DPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) DPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) func.b(ft, fa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case D2D:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) void *ft, *fa, *fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) DPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) DPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) DPFROMREG(fb, NDS32Insn_OPCODE_Rb(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) func.t(ft, fa, fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case D1S:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) void *ft, *fa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) SPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) DPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) func.b(ft, fa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case CD:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned int cmpop = NDS32Insn_OPCODE_BIT69(insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) void *ft, *fa, *fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) SPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) DPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) DPFROMREG(fb, NDS32Insn_OPCODE_Rb(insn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (cmpop < 0x8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) cmpop = cmptab[cmpop];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) fcmpd(ft, fa, fb, cmpop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return SIGILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return SIGILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * If an exception is required, generate a tidy SIGFPE exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #if IS_ENABLED(CONFIG_SUPPORT_DENORMAL_ARITHMETIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (((fpu_reg->fpcsr << 5) & fpu_reg->fpcsr & FPCSR_mskALLE_NO_UDF_IEXE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) || ((fpu_reg->fpcsr << 5) & (fpu_reg->UDF_IEX_trap))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if ((fpu_reg->fpcsr << 5) & fpu_reg->fpcsr & FPCSR_mskALLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return SIGFPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int do_fpuemu(struct pt_regs *regs, struct fpu_struct *fpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned long insn = 0, addr = regs->ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned long emulpc, contpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) unsigned char *pc = (void *)&insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) char c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int i = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (__get_user(c, (unsigned char *)addr++))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return SIGBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *pc++ = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) insn = be32_to_cpu(insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) emulpc = regs->ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) contpc = regs->ipc + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (NDS32Insn_OPCODE(insn) != cop0_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return SIGILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) switch (NDS32Insn_OPCODE_COP0(insn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case fs1_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case fs2_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case fd1_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case fd2_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* a real fpu computation instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ret = fpu_emu(fpu, insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) regs->ipc = contpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return SIGILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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