^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (C) 2017 Andes Technology Corporation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) .data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) .global sp_tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) sp_tmp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) .long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) .globl suspend2ram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) .globl cpu_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) suspend2ram:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) pushm $r0, $r31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #if defined(CONFIG_HWZOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) mfusr $r0, $lc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) mfusr $r1, $le
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) mfusr $r2, $lb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) mfsr $r3, $mr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) mfsr $r4, $mr1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) mfsr $r5, $mr4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) mfsr $r6, $mr6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) mfsr $r7, $mr7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) mfsr $r8, $mr8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) mfsr $r9, $ir0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) mfsr $r10, $ir1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) mfsr $r11, $ir2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) mfsr $r12, $ir3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) mfsr $r13, $ir9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) mfsr $r14, $ir10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) mfsr $r15, $ir12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) mfsr $r16, $ir13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) mfsr $r17, $ir14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) mfsr $r18, $ir15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) pushm $r0, $r19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #if defined(CONFIG_FPU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) jal store_fpu_for_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) tlbop FlushAll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) // transfer $sp from va to pa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) sethi $r0, hi20(PAGE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ori $r0, $r0, lo12(PAGE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) movi $r2, PHYS_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) sub $r1, $sp, $r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) add $r2, $r1, $r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) // store pa($sp) to sp_tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) sethi $r1, hi20(sp_tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) swi $r2, [$r1 + lo12(sp_tmp)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pushm $r16, $r25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pushm $r29, $r30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #ifdef CONFIG_CACHE_L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) jal dcache_wb_all_level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) jal cpu_dcache_wb_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) popm $r29, $r30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) popm $r16, $r25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) // get wake_mask and loop in standby
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) la $r1, wake_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) lwi $r1, [$r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) self_loop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) standby wake_grant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mfsr $r2, $ir15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) and $r2, $r1, $r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) beqz $r2, self_loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) // set ipc to resume address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) la $r1, resume_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) lwi $r1, [$r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mtsr $r1, $ipc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) // reset psw, turn off the address translation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) li $r2, 0x7000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mtsr $r2, $ipsw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) iret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) cpu_resume:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) // translate the address of sp_tmp variable to pa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) la $r1, sp_tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) sethi $r0, hi20(PAGE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ori $r0, $r0, lo12(PAGE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) movi $r2, PHYS_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) sub $r1, $r1, $r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) add $r1, $r1, $r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) // access the sp_tmp to get stack pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) lwi $sp, [$r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) popm $r0, $r19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #if defined(CONFIG_HWZOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mtusr $r0, $lb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) mtusr $r1, $lc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mtusr $r2, $le
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mtsr $r3, $mr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mtsr $r4, $mr1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) mtsr $r5, $mr4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mtsr $r6, $mr6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mtsr $r7, $mr7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mtsr $r8, $mr8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) // set original psw to ipsw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mtsr $r9, $ir1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mtsr $r11, $ir2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mtsr $r12, $ir3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) // set ipc to RR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) la $r13, RR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mtsr $r13, $ir9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mtsr $r14, $ir10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mtsr $r15, $ir12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mtsr $r16, $ir13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mtsr $r17, $ir14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mtsr $r18, $ir15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) popm $r0, $r31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) iret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) RR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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