Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) // Copyright (C) 2005-2017 Andes Technology Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/screen_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_fdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/sections.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/proc-fns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/cache_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/elf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/fpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <nds32_intrinsic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define HWCAP_MFUSR_PC		0x000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define HWCAP_EXT		0x000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define HWCAP_EXT2		0x000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define HWCAP_FPU		0x000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define HWCAP_AUDIO		0x000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define HWCAP_BASE16		0x000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define HWCAP_STRING		0x000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define HWCAP_REDUCED_REGS	0x000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define HWCAP_VIDEO		0x000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define HWCAP_ENCRYPT		0x000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define HWCAP_EDM		0x000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define HWCAP_LMDMA		0x000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define HWCAP_PFM		0x001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define HWCAP_HSMP		0x002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define HWCAP_TRACE		0x004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define HWCAP_DIV		0x008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define HWCAP_MAC		0x010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define HWCAP_L2C		0x020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define HWCAP_FPU_DP		0x040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define HWCAP_V2		0x080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define HWCAP_DX_REGS		0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define HWCAP_HWPRE		0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) unsigned long cpu_id, cpu_rev, cpu_cfgid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) bool has_fpu = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) char cpu_series;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) char *endianness = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) unsigned int __atags_pointer __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) unsigned int elf_hwcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) EXPORT_SYMBOL(elf_hwcap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * The following string table, must sync with HWCAP_xx bitmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * which is defined in <asm/procinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static const char *hwcap_str[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	"mfusr_pc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	"perf1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	"perf2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	"fpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	"audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	"16b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	"string",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	"reduced_regs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	"video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	"encrypt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	"edm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	"lmdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	"pfm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	"hsmp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	"trace",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	"div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	"mac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	"l2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	"fpu_dp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	"v2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	"dx_regs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	"hw_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define WRITE_METHOD "write through"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define WRITE_METHOD "write back"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) struct cache_info L1_cache_info[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static void __init dump_cpu_info(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	int i, p = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	char str[sizeof(hwcap_str) + 16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	for (i = 0; hwcap_str[i]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		if (elf_hwcap & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			sprintf(str + p, "%s ", hwcap_str[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			p += strlen(hwcap_str[i]) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	pr_info("CPU%d Features: %s\n", cpu, str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	L1_cache_info[ICACHE].ways = CACHE_WAY(ICACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	L1_cache_info[ICACHE].line_size = CACHE_LINE_SIZE(ICACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	L1_cache_info[ICACHE].sets = CACHE_SET(ICACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	L1_cache_info[ICACHE].size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	    L1_cache_info[ICACHE].ways * L1_cache_info[ICACHE].line_size *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	    L1_cache_info[ICACHE].sets / 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	pr_info("L1I:%dKB/%dS/%dW/%dB\n", L1_cache_info[ICACHE].size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		L1_cache_info[ICACHE].sets, L1_cache_info[ICACHE].ways,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		L1_cache_info[ICACHE].line_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	L1_cache_info[DCACHE].ways = CACHE_WAY(DCACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	L1_cache_info[DCACHE].line_size = CACHE_LINE_SIZE(DCACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	L1_cache_info[DCACHE].sets = CACHE_SET(DCACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	L1_cache_info[DCACHE].size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	    L1_cache_info[DCACHE].ways * L1_cache_info[DCACHE].line_size *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	    L1_cache_info[DCACHE].sets / 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	pr_info("L1D:%dKB/%dS/%dW/%dB\n", L1_cache_info[DCACHE].size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		L1_cache_info[DCACHE].sets, L1_cache_info[DCACHE].ways,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		L1_cache_info[DCACHE].line_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	pr_info("L1 D-Cache is %s\n", WRITE_METHOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (L1_cache_info[DCACHE].size != L1_CACHE_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		pr_crit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		    ("The cache line size(%d) of this processor is not the same as L1_CACHE_BYTES(%d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		     L1_cache_info[DCACHE].size, L1_CACHE_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #ifdef CONFIG_CPU_CACHE_ALIASING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		int aliasing_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		aliasing_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		    L1_cache_info[ICACHE].size * 1024 / PAGE_SIZE /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		    L1_cache_info[ICACHE].ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		L1_cache_info[ICACHE].aliasing_num = aliasing_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		L1_cache_info[ICACHE].aliasing_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		    (aliasing_num - 1) << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		aliasing_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		    L1_cache_info[DCACHE].size * 1024 / PAGE_SIZE /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		    L1_cache_info[DCACHE].ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		L1_cache_info[DCACHE].aliasing_num = aliasing_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		L1_cache_info[DCACHE].aliasing_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		    (aliasing_num - 1) << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #ifdef CONFIG_FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	/* Disable fpu and enable when it is used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (has_fpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		disable_fpu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void __init setup_cpuinfo(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	unsigned long tmp = 0, cpu_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	cpu_dcache_inval_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	cpu_icache_inval_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	__nds32__isb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	cpu_id = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCPUID) >> CPU_VER_offCPUID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	cpu_name = ((cpu_id) & 0xf0) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	cpu_series = cpu_name ? cpu_name - 10 + 'A' : 'N';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	cpu_id = cpu_id & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	cpu_rev = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskREV) >> CPU_VER_offREV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	cpu_cfgid = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCFGID) >> CPU_VER_offCFGID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	pr_info("CPU:%c%ld, CPU_VER 0x%08x(id %lu, rev %lu, cfg %lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		cpu_series, cpu_id, __nds32__mfsr(NDS32_SR_CPU_VER), cpu_id, cpu_rev, cpu_cfgid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	elf_hwcap |= HWCAP_MFUSR_PC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskBASEV) >> MSC_CFG_offBASEV) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskDIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			elf_hwcap |= HWCAP_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		if ((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskMAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		    || (cpu_id == 12 && cpu_rev < 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			elf_hwcap |= HWCAP_MAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		elf_hwcap |= HWCAP_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		elf_hwcap |= HWCAP_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		elf_hwcap |= HWCAP_MAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (cpu_cfgid & 0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		elf_hwcap |= HWCAP_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (cpu_cfgid & 0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		elf_hwcap |= HWCAP_BASE16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (cpu_cfgid & 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		elf_hwcap |= HWCAP_EXT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (cpu_cfgid & 0x0008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		elf_hwcap |= HWCAP_FPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		has_fpu = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (cpu_cfgid & 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		elf_hwcap |= HWCAP_STRING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (__nds32__mfsr(NDS32_SR_MMU_CFG) & MMU_CFG_mskDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		endianness = "MSB";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		endianness = "LSB";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskEDM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		elf_hwcap |= HWCAP_EDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskLMDMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		elf_hwcap |= HWCAP_LMDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskPFM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		elf_hwcap |= HWCAP_PFM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskHSMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		elf_hwcap |= HWCAP_HSMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskTRACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		elf_hwcap |= HWCAP_TRACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskAUDIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		elf_hwcap |= HWCAP_AUDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		elf_hwcap |= HWCAP_L2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #ifdef CONFIG_HW_PRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (__nds32__mfsr(NDS32_SR_MISC_CTL) & MISC_CTL_makHWPRE_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		elf_hwcap |= HWCAP_HWPRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (!IS_ENABLED(CONFIG_CPU_DCACHE_DISABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		tmp |= CACHE_CTL_mskDC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (!IS_ENABLED(CONFIG_CPU_ICACHE_DISABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		tmp |= CACHE_CTL_mskIC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	__nds32__mtsr_isb(tmp, NDS32_SR_CACHE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	dump_cpu_info(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void __init setup_memory(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	unsigned long ram_start_pfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	unsigned long free_ram_start_pfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	phys_addr_t memory_start, memory_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct memblock_region *region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	memory_end = memory_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/* Find main memory where is the kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	memory_start = memblock_start_of_DRAM();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	memory_end = memblock_end_of_DRAM();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (!memory_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		panic("No memory!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	ram_start_pfn = PFN_UP(memblock_start_of_DRAM());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	/* free_ram_start_pfn is first page after kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	free_ram_start_pfn = PFN_UP(__pa(&_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	max_pfn = PFN_DOWN(memblock_end_of_DRAM());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/* it could update max_pfn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (max_pfn - ram_start_pfn <= MAXMEM_PFN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		max_low_pfn = max_pfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		max_low_pfn = MAXMEM_PFN + ram_start_pfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		if (!IS_ENABLED(CONFIG_HIGHMEM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			max_pfn = MAXMEM_PFN + ram_start_pfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	/* high_memory is related with VMALLOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	high_memory = (void *)__va(max_low_pfn * PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	min_low_pfn = free_ram_start_pfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	 * initialize the boot-time allocator (with low memory only).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	 * This makes the memory from the end of the kernel to the end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	 * RAM usable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	memblock_set_bottom_up(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	memblock_reserve(PFN_PHYS(ram_start_pfn), PFN_PHYS(free_ram_start_pfn - ram_start_pfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	early_init_fdt_reserve_self();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	early_init_fdt_scan_reserved_mem();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	memblock_dump_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) void __init setup_arch(char **cmdline_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	early_init_devtree(__atags_pointer ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		phys_to_virt(__atags_pointer) : __dtb_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	setup_cpuinfo();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	init_mm.start_code = (unsigned long)&_stext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	init_mm.end_code = (unsigned long)&_etext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	init_mm.end_data = (unsigned long)&_edata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	init_mm.brk = (unsigned long)&_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/* setup bootmem allocator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	setup_memory();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	/* paging_init() sets up the MMU and marks all pages as reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	paging_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	/* invalidate all TLB entries because the new mapping is created */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	__nds32__tlbop_flua();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	/* use generic way to parse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	parse_early_param();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	unflatten_and_copy_device_tree();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	*cmdline_p = boot_command_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	early_trap_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int c_show(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	seq_printf(m, "Processor\t: %c%ld (id %lu, rev %lu, cfg %lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		   cpu_series, cpu_id, cpu_id, cpu_rev, cpu_cfgid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	seq_printf(m, "L1I\t\t: %luKB/%luS/%luW/%luB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		   CACHE_SET(ICACHE) * CACHE_WAY(ICACHE) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		   CACHE_LINE_SIZE(ICACHE) / 1024, CACHE_SET(ICACHE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		   CACHE_WAY(ICACHE), CACHE_LINE_SIZE(ICACHE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	seq_printf(m, "L1D\t\t: %luKB/%luS/%luW/%luB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		   CACHE_SET(DCACHE) * CACHE_WAY(DCACHE) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		   CACHE_LINE_SIZE(DCACHE) / 1024, CACHE_SET(DCACHE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		   CACHE_WAY(DCACHE), CACHE_LINE_SIZE(DCACHE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		   loops_per_jiffy / (500000 / HZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		   (loops_per_jiffy / (5000 / HZ)) % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	/* dump out the processor features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	seq_puts(m, "Features\t: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	for (i = 0; hwcap_str[i]; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		if (elf_hwcap & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			seq_printf(m, "%s ", hwcap_str[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	seq_puts(m, "\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static void *c_start(struct seq_file *m, loff_t * pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	return *pos < 1 ? (void *)1 : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void *c_next(struct seq_file *m, void *v, loff_t * pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	++*pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static void c_stop(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct seq_operations cpuinfo_op = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	.start = c_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	.next = c_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	.stop = c_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	.show = c_show
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };